Series STR-F6600INTERIM DATA SHEET
(Subject to change without notice)
February 22, 2000
OFF-LINE QUASI-RESONANTFLYBACK SWITCHING REGULATORS
The Series STR-F6600 is specifically designed to satisfy the require-ments for increased integration and reliability in off-line quasi-resonantflyback converters. The series incorporates a primary control and drivecircuit with discrete avalanche-rated power MOSFETs.
Data Sheet28102.8FDBKOSC.LATCHOCPUVLOOVPTSDCovering the power range from below 25 watts up to 300 watts for100/115/230 VAC inputs, and up to 150 watts for 85 to 265 VACuniversal input, these devices can be used in a range of applications,from battery chargers and set top boxes, to televisions, monitors, andindustrial power supply units.
Cycle-by-cycle current limiting, under-voltage lockout with hyster-esis, over-voltage protection, and thermal shutdown protects the powersupply during the normal overload and fault conditions. Over-voltageprotection and thermal shutdown are latched after a short delay. Thelatch may be reset by cycling the input supply. Low-current startup anda low-power standby mode selected from the secondary circuit completesa comprehensive suite of features. The series is provided in a five-pinovermolded TO-3P style package, affording dielectric isolation withoutcompromising thermal characteristics.
23VIN1OVER-CURRENT& FEEDBACK4Dwg. PK-011-1ABSOLUTE MAXIMUM RATINGSat TA = +25°CControl Supply Voltage, VIN. . . . . . . . 35 VDrain-Source Voltage, VDSSeries STR-F6620. . . . . . . . . . . . 450 VSeries STR-F6630. . . . . . . . . . . . 500 VSeries STR-F6650. . . . . . . . . . . . 650 VSeries STR-F6670. . . . . . . . . . . . 900 VDrain Switching Current, ID. . . See TablePeak Drain Current, IDM. . . . . . See TableAvalanche Energy, EAS. . . . . . . See TableOCP/FB Voltage Range,VOCP. . . . . . . . . . . . . . . -0.3 V to +6 VPackage Power Dissipation, PDcontrol (VIN x IIN(ON)). . . . . . . . . 0.8 Wtotal. . . . . . . . . . . . . . . . . . . See GraphFET Channel Temperature, TJ. . . +150°CInternal Frame Temperature, TF. . +125°COperating Temperature Range,TA. . . . . . . . . . . . . . . -20°C to +125°CStorage Temperature Range,TS. . . . . . . . . . . . . . . . -40°C to +125°CGROUNDSOURCESUPPLYDRAIN5FEATURES
sFlyback Operation with Quasi-Resonant Soft Switchingfor Low Power Dissipation and EMIsRugged Avalanche-Rated MOSFETsChoice of MOSFET Voltage and rDS(on)
sFull Over-Current Protection (no blanking)sUnder-Voltage Lockout with HysteresissOver-Voltage ProtectionsDirect Voltage Feedback
sLow Start-up Current (<400 µA)
sLow-Frequency, Low-Power Standby OperationsOvermolded 5-Pin Package
Always order by complete part number, e.g., STR-F6652 .
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FUNCTIONAL BLOCK DIAGRAM
VIN4DRIVEREG.UVLOOVER-VOLT.PROTECTSREF.RFAULTLATCHQ32DRAINSOURCETSDOSC–rSS+1.45 VFEEDBACK &OVER-CURRENTPROTECTIONcSS–+0.73 V1GROUNDDwg. FK-002-61.0NORMALIZED ALLOWABLE AVALANCHE ENERGY in mJ0.80.6Allowable package power dissipation curves
are shown on page 10.
0.40.20255075100125Dwg. STARTING CHANNEL TEMPERATURE in °C2
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OUTPUT MAXIMUM RATINGS at TA = +25°C
Part NumberSTR-F6624STR-F6626STR-F6628STR-F6632STR-F6652STR-F6653STR-F6654STR-F6656STR-F6672STR-F6674STR-F6676
VDSS (V)450450450500650650650650900900900
rDS(on) (Ω)0.920.580.352.542.81.951.150.717.74.492.81
EAS (mJ)*2043276477.4126260399521163242275
ID (A)†1616229.07.95.69.7164.66.07.8
IDM (A)19263611.2101418256.49.212
POUT (W)
at VIN (V rms)
10012010012010012010012085-26522085-26522085-26522085-26522022022085-26522085-265220
98130145190225290365040865812092190150300
25 (no heatsink)50 (with heat sink)
287644115
* Derate per graph, page 2† Derate per graph, page 12
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ELECTRICAL CHARACTERISTICS at TA = +25°C, VIN = 18 V (unless otherwise specified).
Limits
CharacteristicOn-State VoltageUnder-Voltage LockoutOver-Voltage Threshold
Drain-Source Breakdown VoltageDrain Leakage CurrentOn-State ResistanceMaximum Off Time
Minimum Pulse Duration for Input ofQuasi-Resonant SignalsMinimum Off Time
Feedback Threshold Voltage
SymbolVINTVINQVOVP(th)VBR(DSS)IDSS
Test ConditionsTurn-on, increasing VINTurn-off, decreasing VINTurn-off, increasing VINID = 300 µAAt VDS max
VS = 10 V, ID = 0.9 A, TJ = +25°CDrain waveform highDrain waveform high1Drain waveform high1
Drain waveform low to high1Oscillation synchronized2
Over-Current Protection/FeedbackSink Current
Latch Holding CurrentLatch Release VoltageSwitching TimeSupply Current
IOCP/FBIIN(OVP)VINtfIIN(ON)IIN(OFF)
Insulation RMS Voltage
VWM(RMS)
VOCP/FB = 1.0 V
VIN reduced from 24.5 V to 8.5 VIIN ≤ 20 µA, VIN reduced from 24.5 VVDD = 200 V, ID = 0.9 AOperating3
Increasing VIN prior to oscillationAll terminals simultaneous refer-ence to a metal plate againstthe backside
Output channel to mounting frameMin.14.49.020.5VDS max––45––0.681.31.2–6.6–––2000
Typ.161022.5––––––0.731.451.35––––––
Max.17.61124.5–300see table551.01.50.781.61.54008.425030100–
UnitsVVVVµAΩµsµsµsVVmAµAVnsmAµAV
rDS(ON)
tofftw(th)toffVFDBK
Thermal ResistanceThermal Shutdown
RθJMTJ
–140
––
1.75–
°C/W°C
Notes:Typical Data is for design information only.
1. Feedback is square wave, VIM = 2.2 V, th = 1 µs, tl = 35 µs.
2. For quasi-resonant operation, the input signal must be longer than tw(th) and greater than VFDBK.3. Feedback is square wave, VIM = 2.2 V, th = 4 µs, tl = 1 µs.
4
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Functional Description and Operation
The voltage on the VIN terminal (pin 4) controls startupand shutdown of the Series STR-F6600 devices.Figure 1 shows a typical start up circuit. The VINterminal voltage during startup is shown in figure 2.
At startup, C2 is charged through the startup resistor RS.When the VIN terminal voltage reaches 16 V (typ.), thecontrol circuit enables regulator operation. Once the
regulator starts, it draws up to 30 mA from C2 causing thevoltage on C2 to fall momentarily. Once the regulatoroutput voltage is established, the drive winding D starts tocharge C2 via D2. The voltage on C2 thus recovers to thenominal drive voltage (18 V).
As shown in figure 3, the input current is below 100 µA(at TM = 25°C) prior to control circuit turn on. The latchcircuit holding current is 400 µA (max.). To ensure latchoperation, the current in RS at the lowest ac input voltageshould be at least 500 µA.
IIN30 mA (MAX.)IIN(ON)VINQFigure 1 – Start-Up Circuit
VIN16 VON-STATE VOLTAGE (VINT)(TYP.)100 µA (MAX.)IIN(OFF)11 V(MAX.)VINT14.4 V(MIN.)VINFigure 3 – Supply Terminal Current, IIN
11 V(MAX.)UNDER-VOLTAGE LOCKOUT (VINQ)OPERATION STARTDRIVE WINDINGVOLTAGEThe value of RS thus determines the charge time of C2and thus the startup delay. RS is typicaly 68 kΩ for wideoperation (90 V ac to 265 V ac) and 100 kΩ for 220 voltac operation.
The choice of C2 is a compromise between an accept-able startup delay (in conjunction with RS) and a hold-uptime sufficient to keep pin 4 above its under-voltage
shutdown threshold of 11 V. Typically C2 is in the rangeof 47 µF to 100 µF.
continued, next page...
STARTUPDELAYTIMEFigure 2 – Waveform of VIN Terminal Voltage
at Startup
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Functional Description and Operation (cont’d)
The drive winding voltage is set such that in normaloperation the C2 voltage is above the specified maximumshutdown voltage (11 V) and below the specified mini-mum over-voltage threshold (20.5 V).In applications where there is a significant variation inload current, the VIN terminal voltage may vary, as shownin figure 4. This is due to peak charging of C2. In thiscase, adding a resistor in the range of a few ohms to tens ofohms in series with the rectifier diode D2 will bring thevoltage variation within limits.
VINcomparator output pre-terminates the oscillator, whichturns off the MOSFET drive signal.
The MOSFET is turned on again when either cSS
discharges or a quasi-resonance signal is detected on pin 1.Fixed 50 µs Off-Time: Soft-Start Mode
This is the mode of operation in the absence of a quasi-resonance signal on pin 1 (see figure 5), and occurs at
IOUTFigure 5 – Soft-Start Operation
Figure 4 – Output Current IOUT – Terminal Voltage VIN
Soft Start, Quasi Resonant and Voltage RegulationRefer to the Functional Block Diagram and the TypicalApplication Diagram (figure 6). The internal oscillatoruses the charge/discharge of an internal 4700 pF capacitor(cSS) to generate the MOSFET drive signals.The regulator has two modes of operation:1. fixed 50 µs off time (soft start) and
2. demagnetization sensing quasi-resonant mode —normal operation.
In both cases, voltage regulation is achieved by takingthe composite optocoupled voltage error and superimposeddrain current ramp (current-mode control) and comparingthis to an internal 0.73 V reference. The FBK/OCP
startup and in overload. It also can be commanded exter-nally to provide low-power standby operation.
In the absence of a feedback signal (such as at startup,or a short circuit) the drain current ramp, sensed across R5and noise filtered by R4/C5 appears on pin 1. When theramp voltage on C5 exceeds the 0.73 V reference signal,the FBK/OCP comparator changes state, shutting down theoscillator and turning off the MOSFET. Thus the voltageon cSS is held high (6.5 V) by the comparator. When thecomparator changes state, cSS discharges via rSS; thevoltage on cSS ramps down until it reaches 3.7 V. Theoscillator turns on the MOSFET. This ramp-down time isinternally trimmed to 50 µs. The comparator changes stateagain and the cycle repeats. Thus in the absence of
feedback, the current-sense resistor R5 accurately controlsthe MOSFET maximum current.
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Functional Description and Operation (cont’d)
+ OUTPUT4DRIVEREG.UVLOOVER-VOLT.PROTECTSRFAULTLATCHQ32+VOLTAGESENSEFULL-BRIDGERECTIFIERREF.AC INPUT+TSDOSC+– OUTPUT–+1.45 V–+0.73 V15Dwg. EK-003-5AFigure 6 – Series STR-F6600 Typical Application
WARNING — These devices are designed to be operated at lethal voltages and energy levels. Circuitdesigns that embody these components must conform with applicable safety requirements. Precau-tions must be taken to prevent accidental contact with power-line potentials. Do not connectgrounded test equipment.The use of an isolation transformer is recommended during circuit development and breadboarding.Soft Start with Voltage Feedback (refer to figure 7)Output voltage control is achieved by sensing the opto-coupled feedback current (proportional to the outputvoltage error signal) across resistor R4 and summing thiswith the drain current ramp on R5. The signal on pin 1 istherefore the opposite of the output voltage error signaland the drain current ramp. The dc bias signal across R4 isthus a function of the load. Consequently at light load, thebias signal on R4 is closer to the threshold voltage of thecomparator.
To eliminate the possibility of false shutdown at
MOSFET turn on (when there is a current spike due to thedischarge of primary capacitance), a constant-current sinkof 1.35 mA is turned on, effectively lowering the inputimpedance on pin 1, and momentarily increasing theshutdown threshold.
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Functional Description and Operation (cont’d)
t = π√LpC4VPf R = 1/2π√LpC4VDSVPVINVDS (min)VDFigure 7 - Voltage Regulation Waveforms
Normal Operation (Quasi-Resonant) ModeRefer to the Functional Block Diagram, Typical Appli-cation diagram (figure 6), and Quasi-Resonance Wave-forms (figure 8).
Regulation is achieved as in fixed off-time mode butinstead of having a fixed off-time, the demagnetization ofthe transformer is sensed by a second comparator. Thiscomparator threshold, Vth(2) is nominally 1.45 V. Quasi-resonance sensing makes use of the natural magnetizingand leakage inductances and self-capacitances of thepower circuit.
Figure 8 shows the drain voltage waveform, (VDS), onpin 3 of the STR-F66xx, as well as VP, the voltage on theprimary of the transformer.
Once the current in the output diode stops flowing, theprimary stored energy ‘rings’ as shown by VP and VDS.The resonant frequency (fr) is determined by the magne-tizing inductance of the transformer and the capacitor C4.
VFDBKVOCP ≈ 2.8 VVth(2) ≈ 1.45 VVth(1) ≈ 0.73 VID Dwg. GK-021 Figure 8 – Quasi-Resonance Waveforms
The addition of this capacitor sets the ringing frequencyand reduces the harmonic content in the VDS waveform,lowering EMI. Also since VDS falls to a minimum duringthe first half-cycle of the ring this point can be sensed andused to turn on the MOSFET with minimum voltageacross it. Thus the MOSFET is low voltage and zerocurrent switched (LVS/ZCS).
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Functional Description and Operation (cont’d)
The voltage VOCP (pin 1) has the same form as the VDSwaveform. The condition for quasi-resonant operation isgiven by:
2.0 V < VOCP > 5.5 V for >1 µs
Transformer design is exactly as for any other discon-tinuous-mode type flyback.
For optimum EMI/efficiency performance, quasi-resonance turn off is achieved when the MOSFET is atzero voltage and zero current; that is, at one half cycle ofthe quasi-resonance frequency, fr.
Over-Current Protection (OCP) FunctionsRefer to the Functional Block diagram and TypicalApplication diagram (figure 6).
The regulator implements pulse-by-pulse over-currentprotection, which limits the maximum drain current in theMOSFET on every pulse by switching off the internaldrive to the MOSFET, and the MOSFET drain current isdetected across R5.Drive Circuit
Refer to the Functional Block Diagram.
This circuit is driven from the oscillator and providesthe current drive to charge and discharge the MOSFETgate-source capacitance, thereby switching the device onand off. The basic circuit configuration is totem-pole typewith an additional limiting resistor in the gate circuit atturn on. This limits the turn on speed of the MOSFET,thereby reducing EMI due to the discharge of primarycapacitance. This is possible because of the low-voltageswitching, zero-current switching nature of the turn on.The value of the turn-off resistance is lower, allowingthe device turn-off current to be increased. This reducesthe turn-off loss in the MOSFET.
The gate drive voltage (8.3 V) is such that even with0.73 V across R5 (drain current sense resistor), the
MOSFET is fully enhanced, allowing full use to be madeof its high current handling capacity.
Latch Circuit
The latch circuit keeps the oscillator output low toinhibit operation of the regulator when over-voltage
protection (OVP) and thermal shutdown (TSD) circuits arein operation. As long as the latch hold-in current is
400 µA (max., supplied via RS) with VIN at 8.5 V (pin 4),the regulator will stay in the off state.
An internal noise filter provides 10 µs of noise immu-nity to prevent spurious operation of the over-voltageprotection or thermal shutdown.
With the latch ‘on’, the voltage on pin 4 cycles between16 V and 10 V as shown in figure 9. This is due to thehigher current drawn when the pin 4 is at 16 V comparedto that drawn close to shutdown (10 V).
Pulling VIN (pin 4) below 6.5 V will reset the latchcircuit, re-enabling the regulator.Thermal Shutdown
This internal feature triggers the latch if the internalframe temperature exceeds 140°C (typ.).
The temperature is sensed on the control IC, but alsoprotects against overheating of the MOSFET as the
MOSFET and the control IC are mounted on the same leadframe. Additionally, protection is provided for other on-board components.
VIN16 V(TYP.)10 V(TYP.)TIMEFigure 9 – Example of VIN Terminal Voltage
Waveform at Latch Circuit On
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Functional Description and Operation (cont’d)
Over-Voltage Protection Circuit
This feature of the STR-F66xx triggers the latch circuitwhen the VIN voltage (pin 4) exceeds 22.5 V (typ.).
Because the voltage on pin 4 is proportional to the outputvoltage (they are linked by the transformer turns ratio), theregulator protects the output against over-voltage. Thisfunction is entirely independant of the output-voltageregulation loop and indeed will protect against outputover-voltage should the voltage error signal be lost. Themeasure of over-voltage is given by:
VOUT(OVP) = VOUT(NOM) x VIN(OVP)/VIN(NOM)
where VIN(OVP) is the drive voltage on pin 4.
In an over-voltage sensitive application, the drive
voltage can be set to close to 20 V and thus will protect theoutput, if it rises more than 10% above nominal.
VOUTAC LOWAC HIGHIOUTFigure 10 – Power Supply Output
Overload Characteristics
ALLOWABLE PACKAGE POWER DISSIPATION
STR-F665x60ALLOWABLE PACKAGE POWER DISSIPATION in WATTSSTR-F667x6040ALLOWABLE PACKAGE POWER DISSIPATION in WATTSMOUNTING SURFACETEMPERATURESTR-F6656, 56 W MAX.STR-F6654, 55 W MAX.STR-F6653, 48 W MAX.STR-F6652, 43 W MAX.MOUNTING SURFACETEMPERATURESTR-F6676, 53 W MAX.STR-F6672, 45 W MAX.40RECOMMENDED MAX.FRAME TEMP. = +115°CRECOMMENDED MAX.FRAME TEMP. = +115°C20CONTROLLER0.8 W MAX.FREE AIRALL DEVICES2.8 W MAX.LIMITED BY FRAMETEMP. = +125°C MAX.20CONTROLLER0.8 W MAX.FREE AIRALL DEVICES2.8 W MAX.LIMITED BY FRAMETEMP. = +125°C MAX.02060100TEMPERATURE in °C140Dwg. GK-002060100TEMPERATURE in °C140Dwg. GK-010
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MOSFET Safe Operating Areas(single pulse at TA = +25°C)
STR-F6652
5050STR-F6653
1515LIMITEDBY rDS(on) DRAIN CURRENT in AMPERESDRAIN CURRENT in AMPERES5LIMITEDBY rDS(on) 1.5tw = 0tw .1 = 1ms m Ss SININGLGLE E PPULSULESE51.5tw = 1 ms SINGLE PULSEtw = 0.1 ms SINGLE PULSELIMITEDBYVDSmax0.5TA = +25°C0.150.5TA = +25°C0.150.053.01030100300Dwg. GK0.053.01030100300Dwg. GKDRAIN-SOURCE VOLTAGE in VOLTSDRAIN-SOURCE VOLTAGE in VOLTSSTR-F6654
5050STR-F6656
tw = 0.1 ms Stw IN= 1GL mE s SPUINLSGLEE PULSE15LIMITEDBY rDS(on) 5DRAIN CURRENT in AMPERESDRAIN CURRENT in AMPEREStw = 0.1 ms Stw IN= 1GL mE s SPUINLSGLEE PULSE15LIMITEDBY rDS(on) 51.51.5LIMITEDBYVDSmax0.5TA = +25°C0.150.5TA = +25°C0.150.053.01030100300Dwg. GK0.053.01030100300Dwg. GKDRAIN-SOURCE VOLTAGE in VOLTSDRAIN-SOURCE VOLTAGE in VOLTSLIMITEDBYVDSmaxLIMITEDBYVDSmax11
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MOSFET Safe Operating Areas (cont)
(single pulse at TA = +25°C)
STR-F6672
5050STR-F6676
1515tw = 0.1 ms Stw IN= 1GL mE s SPUINLSGLEE PULSEDRAIN CURRENT in AMPERES5LIMITEDBY rDS(on) 1.5tw = 0.1 ms SItwNG = LE1 m PUs SLSINEGLE PULSEDRAIN CURRENT in AMPERES5LIMITEDBY rDS(on) 1.50.5TA = +25°C0.5TA = +25°C0.150.150.053.01030100300Dwg. GK0.053.01030100300Dwg. GKDRAIN-SOURCE VOLTAGE in VOLTSDRAIN-SOURCE VOLTAGE in VOLTSS.O.A. Derating
1.020Drain Switching Current (ID) Derating
TA = -20°C to +125°CMAXIMUM SWITCHING CURRENT (ID) in AMPERES0.8NORMALIZED SAFE OPERATING AREA16STR-F66560.612STR-F66548.0STR-F6652 & STR-F6672STR-F66534.0STR-F66720.40.20255075100125Dwg. G00.80.91.01.1DwgFRAME TEMPERATURE in °CSOURCE-TO-GROUND VOLTAGE (V2-V5) in VOLTS12
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Transient Thermal Impedance
10STR-F665x10STR-F667x1.0THERMAL IMPEDANCE (ZθJC) in °C/WTHERMAL IMPEDANCE (ZθJC) in °C/W1.0STR-F6652STR-F66530.10.1STR-F6672STR-F66760.010.01STR-F6654STR-F66560.0010.0010.00010.000110 n100 n1 µ10 µ100 µ1 m10 m100 m10 n100 n1 µ10 µ100 µ1 m10 m100 mPOWER PULSE DURATION in SECONDSPOWER PULSE DURATION in SECONDS13
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Applications Information
Capacitors
Electrolytic capacitors carrying large switching fre-quency ripple currents (C1 and the output capacitors)should be capable of handling the high rms currentsinvolved. Capacitors with low ESR are suitable. Thequasi-resonance capacitor C4 should be a high-voltageceramic type suitable for pulsed current operation.The safety critical nature of the off-line applicationmust be considered when selecting both X and Y capaci-tors for common- and differential-mode noise filtering.Use of the low-noise quasi-resonant Series STR-F6600will allow optimization of these capacitor values.C5, the 470 pF filtering capacitor should be a 50 Vtemperature-stable (COG) ceramic type.Resistors
Resistor R5 carries high-frequency current, and so a lowinternal inductance type of 1 W rating should be used.Resistor R9 (RS) should be 2 W metal oxide.All other resistors can be 1/4 watt or 1/2 watt metalfilm.Diodes
Diodes carrying the high-frequency flyback currents(such as the transformer rectifier diodes) should have a fastor ultrafast reverse-recovery characteristic, adequate
current handing and peak reverse-voltage rating. Allegro/Sanken supplies a range of suitable diodes, and these aredescribed in the Allegro/Sanken short-form catalogue(AMS-127) or latest issue of Bulletin D01EC0.Optocoupler
Both Toshiba TLP 621 and Siemens SFH 610A2 or615A2 are suitable. A current-transfer ratio of 50% to200% is acceptable.
Error Amplifier
A standard TL431 transconductance amplifier or anAllegro/Sanken Series SE error-amplifier IC can be used.The Series SE is particularly well-suited to high-voltage(70 V to 140 V) power outputs.
If a Series SE error-amplifier IC is used, normally phasecompensation is not required. Should additional high-frequency attenuation be required, a capacitor (0.022 µF orless) can be connected across the primary side (collector-emitter) of the optocoupler, a diode to maintain quasi-resonant operation should be added in series with thephototransistor emitter.
The products described here are manufactured in Japan by SankenElectric Co., Ltd. for sale by Allegro MicroSystems, Inc.
Sanken Electric Co., Ltd. and Allegro MicroSystems, Inc. reserve theright to make, from time to time, such departures from the detailspecifications as may be required to permit improvements in theperformance, reliability, or manufacturability of their products.Therefore, the user is cautioned to verify that the information in thispublication is current before placing any order.
These products are not authorized for use as critical components inlife-support appliances, devices, or systems without express writtenapproval.
The information included herein is believed to be accurate andreliable. However, Sanken Electric Co., Ltd. and Allegro
MicroSystems, Inc. assume no responsibility for its use; nor for anyinfringements of patents or other rights of third parties which mayresult from its use.
14
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Dimensions in Inches
(for reference only)
0.614±0.008T REF.M0.126ø±0.008 0.216 ±0.0080.136±0.0040.216 ±0.0080.906 ±0.0120.132±0.0040.276±0.0160.2160.033+0.008–0.0040.02615+0.008–0.0040.177±0.0280.100±0.004AT ROOTDwg. MK-003-50 inRecommended mounting hardware torque: 4.34 – 5.79 lbf•ft.
Recommended silicone grease: Dow Corning SC102, Toshiba YG6260, Shin-Etsu G746., or equivalent
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Dimensions in Millimeters
(controlling dimensions)
15.6 ±0.2T REF.M3.2ø±0.25.5±0.23.45±0.15.5 ±0.223.0 ±0.33.35±0.17.0±0.55.50.85+0.2–0.10.6515+0.2–0.14.5±0.72.54±0.1AT ROOTDwg. MK-003-50 mmRecommended mounting hardware torque: 6 – 8 kg•cm or 0.588 – 0.784 Nm.
Recommended silicone grease: Dow Corning SC102, Toshiba YG6260, Shin-Etsu G746., or equivalent
16
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