ICL7104

Precision 41/2 Digit, A/D Converter

DescriptionThe ICL8052 or ICL8068/lCL71C03 chip pairs with theirmultiplexed BCD output and digit drivers are ideally suitedfor the visual display DVM/DPM market. The outstanding41/2 digit accuracy, 200.00mV to 2.0000V full scale capabil-ity, auto-zero and auto-polarity combine with true ratiometricoperation, almost ideal differential linearity and time-provendual slope conversion. Use of these chip pairs eliminatesclock feedthrough problems, and avoids the critical boardlayout usually required to minimize charge injection.When only 2000 counts of resolution are required, the 71C03can be wired for 31/2 digits and give up to 30 readings/sec.,making it ideally suited for a wide variety of applications.The ICL71C03 is an improved CMOS plug-in replacement forthe lCL7103 and should be used in all new designs.Features•Typically Less Than 2µVP-P Noise (200.00mV FullScale, lCL8068)•Accuracy Guaranteed to±1 Count Over Entire±20,000Counts (2.0000V Full Scale)•Guaranteed Zero Reading for 0V Input•True Polarity at Zero Count for Precise Null Detection•Single Reference Voltage Required•Over-Range and Under-Range Signals Available forAuto-Ranging Capability•All Outputs TTL Compatible•Medium Quality Reference, 40ppm (Typ) on Board•Blinking Display Gives Visual Indication of OverRange•Six Auxiliary Inputs/Outputs are Available forInterfacing to UARTs, Microprocessors or OtherComplex Circuitry•5pA Input Current (Typ) (8052A)Ordering InformationPART NUMBER ICL8052CPD lCL8052CDD lCL8052ACPD ICL8052ACDD ICL8068CDD ICL8068ACDD lCL8068ACJD ICL71C03CPl lCL71C03ACPlTEMP.RANGE (oC)0 to 700 to 700 to 700 to 700 to 700 to 700 to 700 to 700 to 70PACKAGE14 Ld PDIP14 Ld CERDIP14 Ld PDIP14 Ld CERDIP14 Ld CERDIP14 Ld CERDIP14 Ld CERDIP28 Ld PDIP28 Ld PDIPPKG.NO.E14.3F14.3E14.3F14.3F14.3F14.3F14.3E28.6E28.6PinoutsICL8052/ICL8068(CERDIP, PDIP)TOP VIEWV+1V-1-1.2VCOMP OUT2REF CAP313+BUFF IN12+INT IN11-INT INVREF10-BUFF IN9BUFF OUTICL8052/8V++ICL806814INT OUT41/2/ 31/22POL3RUN/HOLD4COMP IN5V-6REFERENCE7REF. CAP. 18REF. CAP. 29ANALOG IN10ANALOG GND11CLOCK IN12UNDER-RANGE13OVER-RANGE14ICL71C03 (PDIP)TOP VIEW28BUSY27D1 (LSD)26D225D324D423B8 (MSB)22B421B220B1 (LSB)19D5 (MSD)18STROBE17A-Z IN16A-Z OUT15DIGITAL GNDREF BYPASS4GND5REF OUT6REF SUPPLY7CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.http://www.intersil.com or 407-727-9207|Copyright © Intersil Corporation 1999

File Number

3081.1

3-34

ICL8052/ICL71C03, ICL8068/ICL71C03Functional Block Diagram10kΩ+15V-15V-BUF INREFOUT687110BUFFERBUF OUT9-INT IN11INTEG.INT OUTPOLARITY14COMP.SEVEN-SEGMENTDECODER90kΩ100kΩ0.22µFINT.3REF.300pF10kΩ1kΩ10µFREFCAP 1REFANALOGINPUT10kΩ0.1µFANALOGGND1187410155-A1+ICL8052/8068-A2+-1.2V-A3+23D519MSDD424D325D226D127LSD20B121B222B323B4+BUF IN1310µF (TYP)REFCAP 292+INT IN12COMP1µF (TYP)OUTAZ OUT16AZ INCOMP IN175ZEROCROSSINGDETECTORLATCHLATCHMULTIPLEXERLATCHLATCHLATCHSW36ICL71C03COUNTERSCONTROL LOGIC11564RUN/HOLD12214131828+5V-15VCLOCK4 1/2 DIGIT/OVERUNDERSTROBEBUSYIN3 1/2 DIGITRANGERANGEFIGURE 1.3-35

ICL8052/ICL71C03, ICL8068/ICL71C03Absolute Maximum RatingsICL8052, ICL8068Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .±18VDifferential Input Voltage(8068) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .±30V(8052) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .±6VInput Voltage (Note 1). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .±15VOutput Short Circuit Duration All Outputs (Note 2). . . . . . .IndefiniteICL71C03Power Supply Voltage (GND to V+) . . . . . . . . . . . . . . . . . . . . . 6.5VNegative Supply Voltage (GND to V-). . . . . . . . . . . . . . . . . . . . .-17VAnalog Input Voltage (Note 3) . . . . . . . . . . . . . . . . . . . . . . .V+ to V-Digital Input Voltage (Note 4) . . . . . . . .(GND - 0.3V) to (V+ + 0.3V)Thermal InformationThermal Resistance (Typical, Note 5)θJA (oC/W)θJC (oC/W)CERDIP Package . . . . . . . . . . . . . . . . 752014 Ld PDIP Package. . . . . . . . . . . . . .100N/A28 Ld PDIP Package. . . . . . . . . . . . . .65N/AoMaximum Storage Temperature . . . . . . . . . . . . . . . .-65C to 150oCMaximum Lead Temperature (Soldering, 10s) . . . . . . . . . . . .300oCOperating ConditionsTemperature Range . . . . . . . . . . . . . . . . . . . . . . . . . . . .0oC to 70oCCAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operationof the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.NOTES:1.For supply voltages less than±15V, the absolute maximum input voltage is equal to the supply voltage.2.Short circuit may be to ground or either supply. Rating applies to 70oC ambient temperature.3.Input voltages may exceed the supply voltages provided the input current is limited to±100µA.4.Connecting any digital inputs or outputs to voltages greater then V+ or less than GND may cause destructive device latchup. For thisreason it is recommended that the power supply to the ICL71C03 be established before any inputs from sources not on that supply areapplied.5.θJA is measured with the component mounted on an evaluation PC board in free air.Electrical SpecificationsPARAMETERClock In, Run/Hold, 4 1/2 /3 1/2SYMBOLIINLIINHComp. In CurrentIINLIINHThreshold VoltageAll OutputsB1, B2, B4, B8,D1, D2, D3, D4, D5Busy,Strobe, Over-Range, Under-Range PolaritySwitches 1, 3, 4, 5, 6Switch 2Switch Leakage (All)+5V Supply Range-15V Supply Range+5V Supply Current-15V Supply CurrentPower Dissipation CapacitanceClock Frequency (Note 6)VINTHVOLVOHVOHrDS(ON)rDS(ON)ID(OFF)V+V-I+I-CPDfCLK = 0fCLK = 0vs Clock FrequencyIOL = 1.6mAIOH = -1mAIOH = -10µATESTCONDITIONSVIN = 0VIN = +5VVIN = 0VIN = +5VMIN------2.44.9---4-5---DCTYP0.20.10.10.12.50.254.24.99400120025-151.10.8402000MAX0.6101010-0.40-----6-1833-1200UNITSmAµAµAµAVVVVΩΩpAVVmAmApFkHzNOTE:6.This specification relates to the clock frequency range over which the ICL71C03(A) will correctly perform its various functions. See the“Max Clock Frequency” section under Component Value Selection for limitations on the clock frequency range in a system.3-36

ICL8052/ICL71C03, ICL8068/ICL71C03ICL8068 Electrical SpecificationsVSUPPLY =±15V, TA = 25oC, Unless Otherwise SpecifiedICL8068PARAMETEREACH OPERATIONAL AMPLIFIERInput Offset VoltageInput Current (Either Input) (Note 7)Common-Mode Rejection RatioNon-Linear Component of Common-Mode Rejection Ratio (Note 8)Large Signal Voltage GainSlew RateUnity Gain BandwidthOutput Short-Circuit CurrentCOMPARATOR AMPLIFIERSmall-Signal Voltage GainPositive Output Voltage SwingNegative Output Voltage SwingVOLTAGE REFERENCEOutput VoltageOutput ResistanceTemperature CoefficientSupply Voltage (V++ -V-)Supply Current TotalVOROTCVSUPPLYISUPPLY1.5--±10-1.75550--2.0--±16141.60--±10-1.75540-81.90--±1614VΩppm/oCVmAAVOL+VO-VORL = 30kΩ-12-2.0-13-2.64000---12-2.0-13-2.6---V/VVVAVSRGBWISCVOSIINCMRRVCM = 0VVCM = 0VVCM =±10VVCM =±2VRL = 50kΩ--70-201759011065250----70-20809011065150--mVpAdBdBSYMBOLTESTCONDITIONSMINTYPMAXMINICL8068ATYPMAXUNITS20,000----625----20,000----625----V/VV/µsMHzmAICL8052 Electrical SpecificationsPARAMETEREACH OPERATIONAL AMPLIFIERInput Offset VoltageInput Current (Either Input) (Note 7)Common-Mode Rejection RatioNon-Linear Component of Common-Mode Rejection Ratio (Note 8)Large Signal Voltage GainSlew RateUnity Gain BandwidthOutput Short-Circuit CurrentVSUPPLY =±15V, TA = 25oC, Unless Otherwise SpecifiedTESTCONDITIONSICL8052MINTYPMAXMINICL8052ATYPMAXUNITSSYMBOLVOSIINCMRRVCM = 0VVCM = 0VVCM =±10VVCM =±2V--70-20,000---20590110-61207550--------70-20,000---20290110-61207510------mVpAdBdBV/VV/µsMHzmAAVSRGBWISCRL = 50kΩ3-37

ICL8052/ICL71C03, ICL8068/ICL71C03ICL8052 Electrical SpecificationsPARAMETERCOMPARATOR AMPLIFIERSmall-Signal Voltage GainPositive Output Voltage SwingNegative Output Voltage SwingVOLTAGE REFERENCEOutput VoltageOutput ResistanceTemperature CoefficientSupply Voltage (V++ -V-)Supply Current TotalNOTES:7.The input bias currents are junction leakage currents which approximately double for every 10oC increase in the junction temperature,TJ. Due to limited production test time, the input bias currents are measured with junctions at ambient temperature. In normaloperation the junction temperature rises above the ambient temperature as a result of internal power dissipation, PD.TJ=TA+RθJAPD, where RθJA is the thermal resistance from junction to ambient. A heat sink can be used to reduce temperature rise.8.This is the only component that causes error in dual-slope converter.VOROTCVSUPPLYISUPPLY1.5--±10-1.75550-62.0--±16121.60--±10-1.75540-61.90--±1614VΩppm/oCVmAAVOL+VO-VORL = 30kΩ-12-2.0400013-2.6----12-2.0-13-2.6---V/VVVVSUPPLY =±15V, TA = 25oC, Unless Otherwise Specified (Continued)TESTCONDITIONSICL8052MINTYPMAXMINICL8052ATYPMAXUNITSSYMBOLSystem Electrical Specifications:ICL8068/ICL71C03V++ = +15V, V+ = +5V, V- = -15V, TA = 25oC, fCLK Set for 3 Readings/Sec.ICL8068A/ICL71C03(NOTE 9)MIN-000.00.999--TYP±000.01.0000.20.01MAX+000.01.0011-ICL8068A/ICL71C03(NOTE 10)MIN-000.00.9999--TYP±000.01.00000.50.01MAX000.01.00011-UNITSDigitalReadingDigitalReadingCountsCountsPARAMETERZero Input ReadingRatiometric Error (Note 11)Linearity Over± Full Scale (Error ofReading from Best Straight Line)Differential Linearity (Differencebetween Worst Case Step of AdjacentCounts and Ideal Step)Rollover Error (Difference in Readingfor Equal Positive & Negative VoltageNear Full Scale)Noise (P-P Value Not Exceeded 95%of Time)Leakage Current at InputZero Reading Drift (Note 12)Scale Factor Temperature Coefficient(Note 12)TESTCONDITIONSVIN = 0V,Full Scale = 200mVVIN = VREFFull Scale = 2V-2V≤ VIN≤ +2V-2V≤ VIN≤ +2V-VIN≅ +VIN≈2V-0.21-0.51CountsVIN = 0V,Full Scale = 200mVVIN = 0VVIN = 0V,0oC≤ TA ≤50oCVIN = 2V,0oC≤ TA ≤50oCExt. Ref. 0ppm/oC----320013-300515----21000.52-20025µVpAµV/oCppm/oC3-38

ICL8052/ICL71C03, ICL8068/ICL71C03System Electrical Specifications:ICL8052/ICL71C03V++ = +15V, V+ = +5V, V- = -15V, TA = 25oC, fCLK Set for 3 Reading/Sec.TESTCONDITIONSVIN = 0V,Full Scale = 2VVIN = VREFFull Scale = 2V-2V≤ VIN≤ +2V-2V≤ VIN≤ +2VICL8068A/ICL71C03(NOTE 9)MIN-0.0000.999--TYP±0.0001.0000.20.01MAX+0.0001.0011-ICL8068A/ICL71C03(NOTE 10)MIN-0.0000.9999--TYP±0.0001.00000.50.01MAX0.0001.00011-UNITSDigitalReadingDigitalReadingCountsCountsPARAMETERZero Input ReadingRatiometric Error (Note 11)Linearity Over± Full Scale (Error ofReading from Best Straight Line)Differential Linearity (Differencebetween Worst Case Step of AdjacentCounts and Ideal Step)Rollover Error (Difference in Readingfor Equal Positive & Negative VoltageNear Full Scale)Noise (Peak-To-Peak Value NotExceeded 95% of Time)Leakage Current at InputZero Reading DriftScale Factor Temperature Coefficient-VIN≅ +VIN≈2V-0.21-0.51CountsVIN = 0V,Full Scale = 200mV,Full Scale = 2VVIN = 0VVIN = 0V,0oC To 70oCVIN = 2V,0oC To 70oC,Ext. Ref. 0ppm/oC----2050513--30515-----3030.52--1025µVpAµV/oCppm/oCNOTES:9.Tested in 31/2 digit (2,000 count) circuit shown in Figure 5, clock frequency 12kHz. Pin 2 71C03 connected to GND.10.Tested in 41/2 digit (20,000 count) circuit shown in Figure 5, clock frequency 120kHz. Pin 2 71C03A open.11.Tested with a low dielectric absorption integrating capacitor. See Component Selection Section.12.The temperature range can be extended to 70oC and beyond if the Auto-Zero and Reference capacitors are increased to absorb the hightemperature leakage of the 8068.Detailed DescriptionANALOG SECTIONFigure 2 shows the equivalent Circuit of the Analog Sectionof both the ICL71C03/8052 and the ICL71C03/8068 in the 3different phases of operation. IF the RUN/HOLD pin is leftopen or tied to V+, the system will perform conversions at arate determined by the clock frequency: 40,0002 at 41/2 digitand 4002 at 31/2 digit clock periods per cycle (see Figure 3for details of conversion timing).Auto-zero Phase I(Figure 2A)During the Auto-Zero, the input of the buffer is connected toVREF through switch 2, and switch 3 closes a loop aroundthe integrator and comparator, the purpose of which is tocharge the auto-zero capacitor until the integrator outputdoes not change with time. Also, switches 1 and 2 rechargethe reference capacitor to VREF.Input Integrate Phase II(Figure 2B)During Input Integrate the auto-zero loop is opened and theANALOG INPUT is connected to the BUFFER INPUTthrough switch 4 and CREF. If the input signal is zero, thebuffer, integrator and comparator will see the same voltagethat existed in the previous state (Auto-Zero). Thus, theintegrator output will not change but will remain stationaryduring the entire Input Integrate cycle. If VIN is not equal tozero, and unbalanced condition exists compared to the AutoZero phase, and the integrator will generate a ramp whoseslope is proportional to VIN. At the end of this phase, thesign of the ramp is latched into the polarity F/F.Deintegrate Phase II(Figures 2C and 2D)During the Deintegrate phase, the switch drive logic uses theoutput of the polarity F/F in determining whether to closeswitch 6 or 5. If the input signal is positive, switch 6 is closedand a voltage which is VREF more negative than duringAuto-Zero is impressed on the BUFFER INPUT. NegativeInputs will cause +2(VREF) to be applied to the BUFFERINPUT via switch 5. Thus, the reference capacitor generatesthe equivalent of a (+) or (-) reference from the singlereference voltage with negligible error. The reference voltagereturns the output of the integrator to the zero-crossing pointestablished in Phase I. The time, or number of counts,required to do this is proportional to the input voltage. Sincethe Deintegrate phase can be twice as long as the InputIntegrate Phase, the input voltage required to give a fullscale reading is 2VREF.3-39

ICL8052/ICL71C03, ICL8068/ICL71C03RINTBUFFER4VIN521µFCREF6CINTINTEGRATORVREF(+1.000V)-A1+CSTRAY-A2+CAZCOMPARATOR-A3+ZEROCROSSINGDETECTOR13FIGURE 2A.PHASE I AUTO-ZERORINTVREF(+1.000V)BUFFER4VIN521µFCREF6CINTINTEGRATOR-A1+CSTRAY-A2+CAZCOMPARATOR-A3+ZEROCROSSINGDETECTOR13POLARITYFFFIGURE 2B.PHASE II INTEGRATE INPUTRINTVREF(+1.000V)BUFFER4VIN521µFCREF6CINTINTEGRATOR-A1+CSTRAY-A2+CAZCOMPARATOR-A3+ZEROCROSSINGDETECTOR13POLARITYFFFIGURE 2C.PHASE III + DEINTEGRATERINTVREF(+1.000V)BUFFER4VIN521µFCREF6CINTINTEGRATOR-A1+CSTRAY-A2+CAZCOMPARATOR-A3+ZEROCROSSINGDETECTOR13POLARITYFFFIGURE 2D.PHASE III - DEINTEGRATEFIGURE 2.ANALOG SECTION OF EITHER ICL8052 OR ICL8068 WITH ICL71C033-40

ICL8052/ICL71C03, ICL8068/ICL71C03COUNTSPHASE I41/2 DIGIT31/2 DIGIT10,0011,001POLARITYDETECTEDPHASE II10,0001,000PHASE III20,0012,001ZERO CROSSINGOCCURSZERO CROSSINGDETECTEDINTEGRATOROUTPUTAZ PHASE ICLOCKINT PHASE IIDEINT PHASE IIIAZINTERNAL LATCHBUSY OUTPUTAFTER ZERO CROSSING,ANALOG SECTION WILLBE IN AUTOZEROCONFIGURATIONNUMBER OF COUNTS TO ZERO CROSSINGPROPORTIONAL TO VINFIGURE 3.CONVERSION TIMINGZero-Crossing Flip-FlopFigure 4 shows the problem that the zero-crossing F/F isdesignated to solve.The integrator output is approaching the zero-crossing pointwhere the count will be latched and the reading displayed.For a 20,000 count instrument, the ramp is changingapproximately 0.50mV per clock pulse (10V Max integratoroutput divided by 20,000 counts). The clock pulsefeedthrough superimposed upon this ramp would have to beless than 100mV peak to avoid causing significant errors.The flip-flop interrogates the data once every clock pulseafter the transients of the previous clock pulse and half-clockpulse have died down. False zero-crossings caused by clockpulses are not recognized. Of course, the flip-flop delays thetrue zero-crossing by one count in every instance, and if acorrection were not made, the display would always be onecount too high. Therefore, the counter is disabled for oneclock pulse at the beginning of phase 3. This one countdelay compensates for the delay of the zero crossing flip-flop, and allows the correct number to be latched into thedisplay. Similarly, a one count delay at the beginning ofphase 1 gives an overload display of 0000 instead of 0001.No delay occurs during phase 2, so that true ratiometricreadings result.CLOCKPULSEFEEDTHROUGHDetailed DescriptionDIGITAL SECTIONThe 71C03 includes several pins which allow it to operateconveniently in more sophisticated systems. These include:4-1/2 /3-1/2 (Pin 2)When high (or open) the internal counter operates as a full41/2 decade counter, with a complete measurement cyclerequiring 40,002 counts. When held low, the least significantdecade is cleared and the clock is fed directly into the nextdecade. A measurement cycle now requires only 4,0002clock pulses. All 5 digit drivers are active in either case, witheach digit lasting 200 counts with Pin 2 high (41/2 digit) and20 counts for Pin 2 low (31/2 digit).RUN/HOLD (Pin 4)When high (or open) the A/D will free-run with equallyspaced measurement cycles every 40,0002/4,002 clockpulses. If taken low, the converter will continue the full mea-surement cycle that it is doing and then hold this reading aslong as Pin 4 is held low. A short positive pulse (greater then300ns) will now initiate a new measurement cycle beginningwith up to 10,001/1,001 counts of auto zero. Of course if thepulse occurs before the full measurement cycle(40,002/4,002 counts) is completed, it will not be recognizedand the converter will simply complete the measurement it isdoing. An external indication that full measurement cyclehas been completed is that the firstSTROBE pulse (seebelow) will occur 101/11 counts after the end of this cycle.Thus, if RUN/HOLD is low and has been low for at least101/11 counts, converter is holding and ready to start a newmeasurement when pulsed high.STROBE (Pin 18)This is a negative-going output pulse that aids in transferringthe BCD data to external latches, UARTs or microproces-sors. There are 5 negative-goingSTROBE pulses that occurTRUE ZEROCROSSINGFALSE ZEROCROSSINGFIGURE 4.INTEGRATOR OUTPUT NEAR ZERO-CROSSING3-41

ICL8052/ICL71C03, ICL8068/ICL71C03once and only once for each measurement cycle starting101/11 pulses after the end of the full measurement cycle.Digit 5 (MSD) goes high at the end of the measurementcycle and stays on for 201/21 counts. In the center of thisdigit pulse (to avoid race conditions between changing BCDand digit drives) the firstSTROBE pulse goes negative for1/ clock pulse width. Similarly, after Digit 5, Digit 4 goes2high (for 200/20 clock pulses) and 100/10 pulses later theSTROBE goes negative for the second time. This continuesthrough Digit 1 (LSD) when the fifth and lastSTROBE pulseis sent. The digit drive will continue to scan (unless theprevious signal was over-range) but no additionalSTROBEpulses will be sent until a new measurement is available.Busy (Pin 28)BUSY goes high at the beginning of signal integrate andstays high until the first clock pulse after zero-crossing (orafter end of measurement in the case of an OVER-RANGE).The internal latches are enabled (i.e., loaded) during the firstclock pulse after BUSY and are latched at the end of thisclock pulse. The circuit automatically reverts to auto-zerowhen not BUSY so it may also be considered anA-Z signal.A very simple means for transmitting the data down a singlewire pair from a remote location would be to AND BUSY withclock and subtract 10,001/1,001 counts from the number ofpulses received - as mentioned previously there is one “NO-count” pulse in each Reference Integrate cycle.Over-Range (Pin 4)This pin goes positive when the input signal exceeds therange (20,000/2,000) of the converter. The output F-F is setINTEGRATOROUTPUTAUTOSIGNALZEROREFERENCEINTEG.INTEGRATE10,00110,00020,001 / 2,001/ 1,001/ 1,000COUNTS MAXCOUNTSCOUNTSFULL MEASUREMENT CYCLE40,002/4,002 COUNTSBUSYOVER-RANGEWHEN APPLICABLEUNDER-RANGEWHEN APPLICABLEDIGIT SCANFOROVER-RANGEEXPANDED SCALE BELOWD5D4D3D2D11000†/100 COUNTSSTROBEDIGIT SCANFOR OVER-RANGED5AUTO ZEROat the end of BUSY and is reset to zero at the beginning ofReference Integrate in the next measurement cycle.Under-Range (Pin 13)This pin goes positive when the reading is 9% of range orless. The output F-F is set at the end of BUSY (if the newreading is 1800/180 or less) and is reset a the beginning ofSignal Integrate of the next reading.Polarity (Pin 3)This pin is positive for a positive input signal. It is valid even for azero reading. In other words, +0000 means the signal is posi-tive but less than the least significant bit. The converter can beused as null detector by forcing equal (+) and (-) readings. Thenull at this point should be less than 0.1 LSB. This outputbecomes valid at the beginning of Reference Integrate andremains correct until it is revalidated for the next measurement.Digit Drives (Pins 19, 24, 25, 26, and 27)Each digit drive is a positive-going signal which lasts for200/20 clock pulses. The scan sequence is D5(MSD), D4,D3, D2, and D1 (LSD). All five digits are scanned even whenoperating in the 31/2 digit mode, and this scan is continuousunless and OVER-RANGE occurs. Then all Digit drives areblanked from the end of theSTROBE sequence until thebeginning of Reference Integrate, at which time D5 will startthe scan again. This gives a blinking display as a visualindication of OVER-RANGE.BCD (Pins 20, 21, 22 and 23)The Binary coded decimal bit B8, B4, B2, and B1 are positivelogic signals that go on simultaneously with the Digit driver.†FIRST D5OF AZ AND REF INTONE COUNT LONGERREFERENCEINTEGRATESIGNALINTEGRATED4D3D2D1FIGURE 5.TIMING DIAGRAM FOR OUTPUTS3-42

ICL8052/ICL71C03, ICL8068/ICL71C03Component Value SelectionFor optimum performance of the analog section, care mustbe taken in the selection of values for the integrator capacitorand resistor, auto-zero capacitor, reference voltage, andconversion rate. These values must be chosen to suit theparticular application.Integrating ResistorThe integrating resistor is determined by the full scale inputvoltage and the output current of the buffer used to chargethe integrator capacitor. This current should be smallcompared to the output short circuit current such thatthermal effects are kept to a minimum and linearity is notaffected. Values of 5µA to 40µA give good results with anominal of 20µA. The exact value may be chosen by:Full Scale Voltage (See Note)RINT=------------------------------------------------------------------------------20µANOTE:If gain is used in the buffer amplifier, then:(BufferGain)(Full Scale Voltage)RINT=-------------------------------------------------------------------------------------------20µAAuto-Zero and Reference CapacitorThe size of the auto-zero capacitor has some influence onthe noise of the system, with a larger value capacitor givingless noise. The reference capacitor should be large enoughsuch that stray capacitance to ground from its nodes isnegligible.When gain is used in the buffer amplifier the referencecapacitor should be substantially larger than the auto-zerocapacitor. As a rule of thumb, the reference capacitor shouldbe approximately the gain times the value of the auto-zerocapacitor. The dielectric absorption of the reference cap andauto-zero cap are only important at power-on or when thecircuit is recovering from an overload. Thus, smaller orcheaper caps can be used here if accurate readings are notrequired for the first few seconds of recovery.Reference VoltageThe analog input required to generate a full scale output is:VIN = 2VREF.The stability of the reference voltage is a major factor in theoverall absolute accuracy of the converter. For this reason, itis recommended that an external high quality reference beused where ambient temperature is not controlled or wherehigh-accuracy absolute measurements are being made.Buffer GainAt the end of the auto-zero interval, the instantaneous noisevoltage on the auto-zero capacitor is stored and subtractedfrom the input voltage while adding to the reference voltageduring the next cycle. The result of this is that the noisevoltage is effectively somewhat greater than the input noisevoltage of the buffer itself during integration. By introducingsome voltage gain into the buffer, the effect of the auto-zeronoise (referred to the input) can be reduced to the level ofthe inherent buffer noise. This generally occurs with a buffergain of between 3 and 10. Further increase in buffer gainmerely increases the total offset to be handled by the auto-zero loop, and reduces the available buffer and integratorswings, without improving the noise performance of thesystem. The circuit recommended for doing this with theICL8068/ICL71C03 is shown in Figure 6.Integrating CapacitorThe product of integrating resistor and capacitor is selectedto give 9V swing for full scale inputs. This is a compromisebetween possibly saturating the integrator (at +14V) due totolerance buildup between the resistor, capacitor and clockand the errors a lower voltage swing could induce due tooffsets referred to the output of the comparator. In general,the value of CINT is given by:10,000(4-1/2 Digit)×ClockPeriod×(20µA)1000(3-1/2 Digit)CINT=------------------------------------------------------------------------------------------------------------------------Integrator Output Voltage SwingA very important characteristic of the integrating capacitor isthat it has low dielectric absorption to prevent roll-over orratiometric errors. A good test for dielectric absorption is touse the capacitor with the input tied to the reference.This ratiometric condition should be read half scale 1.0000,and any deviation is probably due to dielectric absorption.Polypropylene capacitors give undetectable errors at reason-able cost. Polystyrene and polycarbonate capacitors may beused in less critical applications.10-50K+15V-15V100kΩ-BUF INREFOUT300pF10kΩ1kΩ5687110BUFFERBUF OUT9-INT IN11INTEG.INT OUT14COMP.INT.3REF.-A1+ICL8068-A2+-1.2V+INT IN12-A3+2COMPOUT+BUF IN13-15VTO ICL7104FIGURE 6.ADDING BUFFER GAIN TO ICL80683-43

ICL8052/ICL71C03, ICL8068/ICL71C03ICL8052 vs ICL8068The ICL8052 offers significantly lower input leakage currentsthan the ICL8068, and may be found preferable in systemswith high input impedances. However, the ICL8068 hassubstantially lower noise voltage, and is the device of choicefor systems where noise is a limiting factor, particularly in lowsignal level conditions.Max Clock FrequencyThe maximum conversion rate of most dual-slope A/Dconverters is limited by frequency response of the compara-tor. The comparator in this circuit is no exception, eventhough it is entirely NPN with an open-loop, gain-bandwidthproduct of 300MHz. The comparator output follows the inte-grator ramp with a 3µs delay, and at a clock frequency of160kHz (6µs period) half of the first reference integrate clockperiod is lost in delay. This means that the meter reading willchange from 0 to 1 with 50µV input, 1 to 2 with 150µV, 2 to 3at 250µV, etc. This transition at midpoint is considereddesirable by most users. However, if the clock frequency isincreased appreciably above 160kHz, the instrument willflash “1” on noise peaks even when the input is shorted.For many dedicated applications where the input signal isalways on one polarity, the dealy of the comparator need notbe limitation. Since the non-linearity and noise do notincrease substantially with frequency, clock rates of up toapproximately 1MHz may be used. For a fixed clockfrequency, the extra count or counts caused by comparatordelay will be a constant and can be subtracted out digitally.The minimum clock frequency is established by leakage onthe auto-zero and reference caps. With most devices,measurement cycles as long as 10 seconds give no measur-able leakage error.To achieve maximum rejection of 60Hz pickup, the signalintegrate cycle should be a multiple of 60Hz. Oscillatorfrequencies of 300kHz, 200kHz, 150kHz, 120kHz, 100kHz,40kHz, 331/3kHz, etc, should be selected. For 50Hzrejection, oscillator frequencies of 250kHz, 1662/3kHz,125kHz, 100kHz, etc. would be suitable. Note that 100kHz(2.5 readings/second) will reject both 50Hz and 60Hz.The clock used should be free from significant phase orfrequency jitter. A simple two-gate oscillator and one basedon CMOS 7555 timer are shown in the Applications section.The multiplexed output means that if the display takessignificant current from the logic supply, the clock shouldhave good PSRR.LED is driven from the 7-segment decoder, with a zeroreading blanked by connecting a D5 signal to RBI input ofthe decoder.A voltage translation network is connected between the com-parator output of the 8068/52 and the auto-zero input of the71C03. The purpose of this network is to assure that, duringauto-zero, the output of the comparator is at or near thethreshold of the 71C03 logic (+2.5V) while the auto-zerocapacitor is being charged to VREF (+100mV for a 200mVinstrument). Otherwise, even with 0V in, some reference inte-grate period would be required to drive the comparator outputto the threshold level. This would show up as an equivalentoffset error. Once the divider network has been selected, theunit-to-unit variation should contribute less than a tenth of acount error. A second feature is the back-to-back diodes, usedto lower the noise. In the normal operating mode they offer ahigh impedance and long integrating time constant to anynoise pulses charging the auto-zero cap. At startup or recov-ery from an overload, their impedance is low to large signalsso that the cap can be charged up in one auto-zero cycle. Thebuffer gain does not have to be set precisely at 10 since thegain is used in both the integrate and deintegrate phase. Forscale factors other then 200mV the gain of the buffer shouldbe changed to give a±2V buffer output. For 2.0000V full scalethis means unity gain and for 20,000mV (1µV resolution) again of 100 is necessary. Not all 8068As can operate properlyat a gain of 100 since their offset should be less than 10mV inorder to accommodate the auto-zero circuitry. However, fordevices selected with less than 10mV offset, the noise perfor-mance is reasonable with approximately 1.5µV near full scale.On all scales less than 200mV, the voltage translation networkshould be made adjustable as an offset trim.The auto-zero cap should be 1µF for all scales and the refer-ence capacitor should be 1µF times the gain of the bufferamplifier. At this value if the input leakages of the 8052/8068are equal, the droop effects will cancel giving zero offset.This is especially important at high temperature. Sometypical component values are shown in Table 1. For 31/2 digitconversion, use 12kHz clock.V++ = +15V, V+ = 5V, V- = -15VClock Freq. = 120kHz (41/2 Digit) or 12kHz (31/2 Digit)TABLE 1.SPECIFICATIONFull Scale VINBuffer Gain(RB1+RB2)-----------------------------------RB2RINTCINTCAZCREFVREFResolution (41/2 Digit)20100(SeeNote)1000.221.010101VALVE2001020001UNITSmVV/VApplicationsSpecific Circuits Using the 8068/71C03 8052/71C03Figure 7 shows the complete circuit for a±41/2 digit(±200mV full scale) A/D converter with LED readout usingthe internal reference of the 8068/52. If an externalreference is used, the reference supply (pin 7) should beconnected to ground and the 300pF reference cap deleted.The circuit also shows a typical RC input filter. Depending onthe application, the time-constant of this filter can be madefaster, slower, or the filter deleted completely. The1/2 digit1000.221.010100101000.221.01.01000100kΩµFµFµFmVµVNOTE:Comment on offset limitations above. Buffer gain does notimprove ICL8052 noise performance adequately.3-44

ICL8052/ICL71C03, ICL8068/ICL71C03+5V5150Ω4.7kΩ150Ω4321150Ω7447abB1cB2dB3eB4fgRBIICL71C03+5V1V+241/2/ 31/23POLARITY4RUN/HOLD5COMP INBUSY28(LSD) D127D226D325D424(MSB) B823B422B221 (LSB) B120 (MSD) D519STROBE18A-Z IN17A-Z OUT16300kΩ-15V36kΩ10kΩ10µF1kΩ-15V300µF47kΩ-15V10µF10kΩSIGNALINPUT0.1µF6V-7REFERENCE8REF. CAP. 19REF. CAP. 210ANALOG IN11ANALOG GND12CLOCK IN13UNDER-RANGE1.0µFICL80680.22µF1V-2COMP OUT3REF CAP4REF BYPASS5GND6REF OUTINT OUT14+BUFF IN13+INT IN12-INT IN11-BUFF IN10BUFF OUT9V++8100kΩ90kΩ10kΩ14OVER-RANGEDIGITAL GND15CLOCKIN120kHz = 3READINGS/SEC7REF SUPPLY+15VNOTE:For 31/2 digit, tie pin 2 low and change clock to 12kHz.FIGURE 7.ICL8052A (8068A)/71C03A 41/2 DIGIT A/D CONVERTERaPOLaDM8880V+3kΩ+5Vg+5V5kΩHI VOLTAGE BUFFER DI 50547kΩ0.02µFgRBIBIDPROG0VA2.5kΩGATESARE74090.02µF0.02µF0.02µF0.02µFPOLD58052A/8068AD4D3D2D171C03AB8B4B2B1FIGURE 8.ICL8052-8068/71C03A PLASMA DISPLAY CIRCUIT3-45

ICL8052/ICL71C03, ICL8068/ICL71C03A suitable circuit for driving a plasma-type display is shownin Figure 8. The high voltage anode driver buffer is made byDionics. The 3 AND gates and caps driving “Bl” are neededfor interdigit blanking of multiple-digit display elements, andcan be omitted if not needed. The 2K and 3K resistors setthe current levels in the display. A similar arrangement canbe used with “Nixie®” tubes.Nixie® is a registered trademark of Burroughs Corporation.driver circuit could be ganged to the one shown if required.This would be useful if additional annunciators were needed.Figure 10 shows the complete circuit for a 41/2 digit(±2.000V) A/D, again using the internal reference of the8052A/8068A.Figure 11 shows a more complicated circuit for driving LCDdisplays. Here the data is latched into the ICM7211 by theSTROBE signal and “Overrange” is indicated by blanking the4 digits. A clock oscillator circuit using the ICM7555 CMOStimer is shown. Some other suitable clock circuits are sug-gested in Figures 12 and 13. The 2-gate circuit should useCMOS gates to maintain good power supply rejection.A problem sometimes encountered with the 8052/68/71C03A/D is that of gross over-voltage applied in the input. Voltagein excess of ±2.000V may cause the integrator output tosaturate. When this occurs, the integrator can no longersource (or sink) the current required to hold the summingjunction (Pin 11) at the voltage stored on the auto zerocapacitor. As a result, the voltage across the integratorcapacitor decreases sufficiently to give a false voltagereading. This problem can also show up as large-signalinstability on overrange conditions. A simple solution to thisproblem is to use junction FET transistors across theintegrator capacitor to source (or sink) current into thesumming junction and prevent the integrator amplifier fromsaturating, as shown in Figure 14.Analog and Digital GroundsExtreme care must be taken to avoid ground loops in thelayout of 8068 or 8052/71C03A circuits, especially in highsensitivity circuits. It is most important that return currentsfrom digital loads are not fed into the analog ground line. Bothof the above circuits have considerable current flowing in thedigital ground returns from drivers, etc. A recommended con-nection sequence for the ground lines is shown in Figure 9.Other Circuits for Display ApplicationsPopular LCD displays can be interfaced to the Output of theICL71C03 with suitable display drivers, such as theICM7211A as shown in Figure 10. A standard CMOS 4000series LCD driver circuit is used for displaying the1/2 digit,the polarity, and the “over-range” flag. A similar circuit can beused with the ICM7212A LED driver. Of course, another fullBUFFOUTPIN 11ICL71C03AN GNDBUFF-IN(IF USED)REFVOLTAGEVREFEXTERNALREFERENCE(IF USED)ANALOG SUPPLYBYPASS CAPACITORS+15V-15V+VIN-I/PFILTERCAPCAZPIN 5ICL8052/68AN GNDANALOGSUPPLYRETURNBOARDEDGEDIGITALSUPPLYRETURN8068 PIN 2COMPARATORDIGITALLOGICDIG GNDICL7104PIN 2DEVICE PIN+5V SUPPLY BYPASS CAPACITOR(S)FIGURE 9.GROUNDING SEQUENCE3-46

ICL8052/ICL71C03, ICL8068/ICL71C0341/2 DIGIT LCD DISPLAY28 SEGMENTSD1 - D4+5V116151412534CD4054A781311109260V+5V1V+241/2 / 31/23POL4R/H5COMP IN-15V6V-7REF8REF. CAP. 11µF100kΩINPUT0.1µF9REF. CAP. 210INPUTICL71C03BUSY28D127D226D325D424B823B422B221B120D5190VICM7211A5 BP31 D132 D233 D334 D430 B3OPTIONALCAPACITOR+5V28 B1OSC 3622-100pF27 B029 B235 V-V+ 1+5V2, 3, 46 - 2637 - 40BACKPLANE11ANALOG GNDSTROBE1812CLOCK13UR14ORA-Z IN17A-Z OUT16DIG GND150VCLOCK IN (120kHz = 3 READINGS/SEC)1.0µF-15V300µF1234ICL8052 (A)8068 (A)141312111098+15V100kΩ0.22µF36kΩ300kΩ-15V5kΩ10kΩ56710µFANALOG GNDFIGURE 10.DRIVING LCD DISPLAYS3-47

ICL8052/ICL71C03, ICL8068/ICL71C03+5V41/2DIGIT LCD DISPLAY28 SEGMENTSD1 - D41/ CD40302BACKPLANE+5V1V+ICL71C03(A)BUSY28D127D226D325D424B823B422B221B120D519CD4071CD4071CD40811/ CD40304ICM7211A5 BP31 D132 D233 D334 D430 B329 B228 B127 B035 V-0V+5V1/ CD40304241/2 / 31/23POL4R/H5COMP IN-15V6V-7REF1µF100kΩINPUT0.1µF8REF. CAP. 19REF. CAP. 210INPUT2, 3, 46 - 2637 - 40OPTIONALCAPACITOR+5VOSC 3622-100pFV+ 1+5V11ANALOG GNDSTROBE1812CLOCK13UR14ORA-Z IN17A-Z OUT16DIG GND150V+5V4.7kΩ0V1V-2ICM7555V+876510 TO 15kΩADJUST TOFCL = 120kHz1.0µF+5V-15V300µF36kΩ1234300kΩ-15V5kΩ10kΩ10µF567ICL8052 (A)8068 (A)141312111098+15V100kΩ0.22µF3OUT4RESET300pF0VANALOG GNDFIGURE 11.41/2 DIGIT LCD DPM WITH DIGIT BLANKING ON OVERRANGE3-48

ICL8052/ICL71C03, ICL8068/ICL71C03+5V16kΩ56kΩ20.22µFfOSC = 0.45/RC+87LM3111-3416kΩ390pF1kΩ30kΩR37.5kΩC100pFFIGURE 12.CMOS OSCILLATORFIGURE 13.LM311 OSCILLATORDD+15V-15V-BUF INREFOUT300pFREFCOMP5687110BUFFER100KBUF OUT90.22µFS2N5461S2N5458-INT IN11INTEG.INT OUT14COMP.INT.3REF.-A1+8052A/8068A-A2+-1.2V-A3+2COMPOUT+BUF IN13+INT IN12TO ICL71C03FIGURE 14.GROSS OVERVOLTAGE PROTECTION CIRCUITInterfacing with UARTs andMicroprocessorsFigure 15 shows a very simple interface between a free-run-ning 8068/8052/71C03A and a UART. The fiveSTROBEpulses start the transmission of the five data words. The digit5 word is 0000XXXX, digit 4 is 1000XXXX, digit 3 is0100XXXX, etc. Also, the polarity is transmitted indirectly byusing it to drive the Even Parity Enable Pin (EPE). If EPE ofthe receiver is held low, a parity flag at the receiver can bedecoded as a positive signal, no flag as negative. A complexarrangement is shown in Figure 14. Here the UART caninstruct the A/D to begin a measurement sequence by aword on RRI. The Busy signal resets the Data Ready Reset(DRR). AgainSTROBE starts the transmit sequence. Aquad 2 input multiplexer is used to superimpose polarity,over-range, and under-range onto the D5 word since in thisinstance it is known that B2 = B4 = B8 = 0.For correct operation it is important that the UART clock befast enough that each word is transmitted before the nextSTROBE pulse arrives. Parity is locked into the UART atload time but does not change in this connection during anoutput stream.Circuits to interface the 71C03(A) directly with three popularmicroprocessors are shown in Figures 17, 18 and 19. Themain differences in the circuits are that the IM6100 with its12-bit word capability can accept polarity, over-range, under-range, 4 bits of BCD and 5 digits simultaneously where the8080/8048 and the MC6800 groups with 8-bit words need tohave polarity, over-range and under-range multiplexed ontothe Digit 5 word - as in the UART circuits. In each case themicroprocessor can instruct the A/D when to begin a mea-surement and when to hold this measurement.Application NotesNOTE #AN016AN017AN018DESCRIPTION“Selecting A/D Converters”“The Integrating A/D Converter”“Do’s and Don’ts of Applying A/DConverters”“Low Cost Digital Panel Meter Designs”“Build an Auto-Ranging DMM Using the8052A/7103A A/D Converter Pair,” byLarry GoffAnswerFAXDOC. #901690179018AN023AN028902390283-49

ICL8052/ICL71C03, ICL8068/ICL71C03SERIAL OUTPUTTO RECEIVING UARTTROUARTIM6402/3EPETBR12345678TBRLD4NCD5D3D2D1B1B2B4B8STROBE71C03/APOLRUN/HOLD+5VFIGURE 15.SIMPLE ICL71C03/71C03A TO UART INTERFACETRORRIUARTIM6402/3DRRDRTBRL5678EPETBR12341Y2Y3YENABLE74C1571A2A3ASELECT1B2B3BD4D5D3D2D1B1B2B4B8POLOVERUNDER71C03/ASTROBERUN/HOLDBUSY100pF10kΩ+5VFIGURE 16.COMPLEX ICL71C03/7103A TO UART INTERFACE3-50

ICL8052/ICL71C03, ICL8068/ICL71C031212180C951580C9515112READ 1IM6101D1D2D3D4D5B1B2B4B8POLOVER71C03/ASTROBERUN/HOLDSENSE 17WRITE 1IM6100FIGURE 17.IM6100 TO ICL71C03A/71C03A INTERFACEEN74C1571Y2YPA0PA1PA2PA3MC680XORMCS650XEN74C1571Y2YPA0PA1PA2PA38255(MODE 1)PA4PA5PA6PA7STBAPB08080,8085,ETC.1B2B3BSEL1A2A3A3Y1B2B3BSEL1A2A3A3YRUN/HOLDD5B8B4B2B1D171C03D2D3D4STROBEPOLOVERPOLUNDEROVERPA4PA5PA6PA7CA1CA2RUN/HOLDFIGURE 18.ICL71C03 TO MC6800, MCS650X INTERFACEFIGURE 19.ICL71C03 TO MCS-48, -80, -85 INTERFACE3-51

UNDERMC6820D5B8B4B2B1D171C03D2D3D4STROBEICL8052/ICL71C03, ICL8068/ICL71C03ICL71C03 with ICL8052/8068 Integrating A/D Converter EquationsThe ICL71C03 does not have an internal crystal or RCoscillator. It has a clock input only.Integration Period10,000-(4-1/2 Digit)tINT=--------------------fCLOCK1,000-(3-1/2 Digit)tINT=--------------------fCLOCKIntegrator Output Voltage(tINT)(IINT)VINT=-------------------------------CINTVINT (Typ) = 9VOutput CountVINCount=10,000×--------------(4-1/2 Digit)VREFVINCount=1,000×--------------(3-1/2 Digit)VREFNOTE:The 41/2 digit mode’s LSD will be output as a zero in the 31/2digit mode.Integration Clock PeriodtCLOCK = 1/fCLOCK60/50Hz Rejection CriteriontINT/t60Hz or tINT/t50Hz = IntegerOptimum Integration CurrentIINT = 20µAFull Scale Analog Input VoltageVINFS (Typ) = 200mV to 2.0V = 2VREFIntegrate Resistor(BufferGain)×VINFS-RINT=------------------------------------------------------------IINTOutput Type:4 Nibbles BCD with Polarity and Over-range.Power Supply:±15V, +5VV++ = +15VV- = -15VV+ = +5VVREF≅ 1.75VIf VREF not used, float output pin.Auto Zero Capacitor Values0.01µF < CAZ < 1µFReference Capacitor ValueCREF = (Buffer Gain) x CAZIntegrate Capacitor(tINT)(IINT)CINT=-------------------------------VINTAUTO ZERO(COUNTS)30,001 - 10,0013,001 - 1,001INTEGRATE(FIXED COUNT)10,0001,000DEINTEGRATE(COUNTS)1 - 20,0011 - 2,001(41/2 DIGIT)(31/2 DIGIT)TOTAL CONVERSION TIME (tCONV)(IN CONTINUOUS MODE)tCONV= 40,002 * tCLOCK (41/2 DIGIT MODE)tCONV= 4,002 * tCLOCK (31/2 DIGIT MODE)FIGURE 20.INTEGRATOR OUTPUTAll Intersil semiconductor products are manufactured, assembled and tested underISO9000 quality systems certification.Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time withoutnotice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurateand reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties whichmay result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.For information regarding Intersil Corporation and its products, see web sitehttp://www.intersil.com3-52