专利名称：PACKAGING CONFIGURATIONS FOR
VERTICAL ELECTRONIC DEVICES USINGCONDUCTIVE TRACES DISPOSED ONLAMINATED BOARD LAYERS
发明人：Ming Sun,Yueh Se Ho申请号：US13454342申请日：20120424
公开号：US20120205803A1公开日：20120816
专利附图：
摘要：This invention discloses an electronic package for containing a vertical
semiconductor chip that includes a laminated board having a via connector and
conductive traces distributed on multiple layers of the laminated board connected to thevia connector. The semiconductor chip having at least one electrode connected to theconductive traces for electrically connected to the conductive traces at a different layeron the laminated board and the via connector dissipating heat generated from thevertical semiconductor. A ball grid array (BGA) connected to the via connector functioningas contact at a bottom surface of the package for mounting on electrical terminalsdisposed on a printed circuit board (PCB) wherein the laminated board having a thermalexpansion coefficient in substantially a same range the PCB whereby the BGA having areliable electrical contact with the electrical terminals.
申请人：Ming Sun,Yueh Se Ho
地址：Sunnyvale CA US,Sunnyvale CA US
国籍：US,US
更多信息请下载全文后查看
因篇幅问题不能全部显示，请点此查看更多更全内容