White Electronic DesignsW3EG6433S-D3
-JD3
PRELIMINARY*
256MB – 2x16Mx64 DDR SDRAM UNBUFFERED
FEATURES
DDR266 and DDR333 Double-data-rate architecture Bi-directional data strobes (DQS) Differential clock inputs (CK & CK#) Programmable Read Latency 2,2.5 (clock) Programmable Burst Length (2,4,8)
Programmable Burst type (sequential & interleave) Edge aligned data output, center aligned data input. Auto and self refresh Serial presence detect Dual Rank
Power supply: 2.5V ± 0.2V JEDEC 184 pin DIMM package
• JD3 PCB height: 30.48 (1.20\")
NOTE: Consult factory for availability of:
• RoHS compliant products • Vendor source control options • Industrial temperature option
* This product is under development, is not qualifi ed or characterized and is subject to change without notice.
DESCRIPTION
The W3EG6433S is a 2x16Mx64 Double Data Rate SDRAM memory module based on 256Mb DDR SDRAM component. The module consists of sixteen 16Mx8 DDR SDRAMs in 66 pin TSOP packages mounted on a 184 pin FR4 substrate.
Synchronous design allows precise cycle control with the use of system clock. Data I/O transactions are possible on both edges and Burst Lengths allow the same device to be useful for a variety of high bandwidth, high performance memory system applications.
OPERATING FREQUENCIES
DDR333@CL=2.5
Clock SpeedCL-tRCD-tRP
166MHz2.5-3-3
DDR266 @CL=2
133MHz2-2-2
DDR266 @CL=2
133MHz2-3-3
DDR266 @CL=2.5
133MHz2.5-3-3
November 2005Rev. 2
1White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
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White Electronic DesignsPIN CONFIGURATION
PIN12345678910111213141516171819202122232425262728293031323334353637383940414243444546
SYMBOLVREFDQ0VSSDQ1DQS0DQ2VCCDQ3NCNCVSSDQ8DQ9DQS1VCCQCK1CK1#VSSDQ10DQ11CKE0VCCQDQ16DQ17DQS2VSSA9DQ18A7VCCQDQ19A5DQ24VSSDQ25DQS3A4VCCDQ26DQ27A2VSSA1NCNCVCC
PIN47484950515253545556575859606162636465666768697071727374757677787980818283848586878889909192
SYMBOLNCA0NCVSSNCBA1DQ32VCCQDQ33DQS4DQ34VSSBA0DQ35DQ40VCCQWE#DQ41CAS#VSSDQS5DQ42DQ43VCCNCDQ48DQ49VSSCK2#CK2VCCQDQS6DQ50DQ51VSSVCCIDDQ56DQ57VCCDQS7DQ58DQ59VSSNCSDASCL
PIN93949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138
SYMBOLVSSDQ4DQ5VCCQDQM0DQ6DQ7VSSNCNCNCVCCQDQ12DQ13DQM1VCCDQ14DQ15CKE1VCCQNCDQ20NCVSSDQ21A11DM2VCCDQ22A8DQ23VSSA6DQ28DQ29VCCQDM3A3D30VSSDQ31NCNCVCCQCK0CK0#
PIN139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184
SYMBOLVSSNCA10NCVCCQNCVSSDQ36DQ37VCCDM4DQ38DQ39VSSDQ44RAS#DQ45VCCQCS0#CS1#DM5VSSDQ46DQ47NCVCCQDQ52DQ53NCVCCDQM6DQ54DQ55VCCQNCDQ60DQ61VSSDM7DQ62DQ63VCCQSA0SA1SA2VCCSPD
A0-A11BA0-BA1DQ0-DQ63DQS0-DQS8CK0, CK1, CK2CK0#CK1#, CK2#CKE0, CKE1CS0#, CS1#RAS#CAS#WE#DM0-DM7VCCVCCQVSSVREFVCCSPDSDASCLSA0-SA2NC
W3EG6433S-D3
-JD3
PRELIMINARY
PIN NAMES
Address input (Multiplexed)Bank Select AddressData Input/Output
Data Strobe Input/OutputClock InputClock Input
Clock Enable inputChip Select InputRow Address StrobeColumn Address StrobeWrite EnableData-in-maskPower Supply
Power Supply for DQSGround
Power Supply for ReferenceSerial EEPROM Power SupplySerial data I/OSerial clock
Address in EEPROMNo Connect
November 2005Rev. 2
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White Electronic DesignsFUNCTIONAL BLOCK DIAGRAMCS1#CS0#DQS0DM0DM#CS#DQSDM#CS#DQSW3EG6433S-D3
-JD3
PRELIMINARY
DQS4DM4DM#CS#DQSDM#CS#DQSDQ0DQ1DQ2DQ3DQ4DQ5DQ6DQ7DQS1DM1I/O 7I/O 6I/O 1I/O 0I/O 5I/O 4I/O 3I/O 2I/O 0I/O 1I/O 6I/O 7I/O 2I/O 3I/O 4I/O 5DQS5DM5DQ32DQ33DQ34DQ35DQ36DQ37DQ38DQ39I/O 7I/O 6I/O 1I/O 0I/O 5I/O 4I/O 3I/O 2I/O 0I/O 1I/O 6I/O 7I/O 2I/O 3I/O 4I/O 5DM#CS#DQSDM#CS#DQSDM#CS#DQSDM#CS#DQSDQ8DQ9DQ10DQ11DQ12DQ13DQ14DQ15DQS2DM2I/O 7I/O 6I/O 1I/O 0I/O 5I/O 4I/O 3I/O 2I/O 0I/O 1I/O 6I/O 7I/O 2I/O 3I/O 4I/O 5DQS6DM6DQ40DQ41DQ42DQ43DQ44DQ45DQ46DQ47I/O 7I/O 6I/O 1I/O 0I/O 5I/O 4I/O 3I/O 2I/O 0I/O 1I/O 6I/O 7I/O 2I/O 3I/O 4I/O 5DM#CS#DQSDM#CS#DQSDM#CS#DQSDM#CS#DQSDQ16DQ17DQ18DQ19DQ20DQ21DQ22DQ23DQS3DM3I/O 7I/O 6I/O 1I/O 0I/O 5I/O 4I/O 3I/O 2I/O 0I/O 1I/O 6I/O 7I/O 2I/O 3I/O 4I/O 5DQS7DM7DQ48DQ49DQ50DQ51DQ52DQ53DQ54DQ55I/O 7I/O 6I/O 1I/O 0I/O 5I/O 4I/O 3I/O 2I/O 0I/O 1I/O 6I/O 7I/O 2I/O 3I/O 4I/O 5DM#CS#DQSDM#CS#DQSDM#CS#DQSDM#CS#DQSDQ24DQ25DQ26DQ27DQ28DQ29DQ30DQ31I/O 7I/O 6I/O 1I/O 0I/O 5I/O 4I/O 3I/O 2I/O 0I/O 1I/O 6I/O 7I/O 2I/O 3I/O 4I/O 5DQ56DQ57DQ58DQ59DQ60DQ61DQ62DQ63I/O 7I/O 6I/O 1I/O 0I/O 5I/O 4I/O 3I/O 2I/O 0I/O 1I/O 6I/O 7I/O 2I/O 3I/O 4I/O 5DDR SDRAMsVCCSPDSPDDDR SDRAMsDDR SDRAMsDDR SDRAMsVREFVSSDDR SDRAMsDDR SDRAMsSerial PDSCLWPA0SA0A1SA1A2SA2SDAVCC/VCCQR=120ΩCK0/1/2CK0/1/2#CardEdge*DDR SDRAMs*DDR SDRAMsDDR SDRAMsDDR SDRAMsBA0 - BA1A0 - A11RAS#CAS#CKE0/1WE#BA0-BA1 : DDR SDRAMs A0-A11 : DDR SDRAMs RAS# : DDR SDRAMs CAS# : DDR SDRAMsCKE : DDR SDRAMs WE# : DDR SDRAMs Clock Input* Clock WiringDDR SDRAMs*CK0/CK0#4 DDR SDRAMs*CK1/CK1#6 DDR SDRAMs*CK2/CK2#6 DDR SDRAMs*Clock Net WiringNotes : 1. DQ-to-I/O wiring is shown as recommended but may be changed.2. DQ/DQS/DM/CKE/CS# relationships must be maintained as shown.3. DQ, DQS, DM#/DQS# resistors: 22 Ohms + 5%.4. BAx, Ax, RAS#, CAS#, WE# resistors: 3 Ohms + 5%.November 2005Rev. 23White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com元器件交易网www.cecb2b.com
White Electronic DesignsABSOLUTE MAXIMUM RATINGS
Parameter
Voltage on any pin relative to VSSVoltage on VCC supply relative to VSSStorage TemperaturePower DissipationShort Circuit Current
Note:
W3EG6433S-D3
-JD3
PRELIMINARY
SymbolVIN, VOUTVCC, VCCQTSTGPDIOS
Value-0.5 to 3.6-1.0 to 3.6-55 to +150
2450
UnitsVV°C WmA
Permanent device damage may occur if ‘ABSOLUTE MAXIMUM RATINGS’ are exceeded.Functional operation should be restricted to recommended operating condition.
Exposure to higher than recommended voltage for extended periods of time could affect device reliability
DC OPERATING CONDITIONS
Recommended perating conditions (Voltage referenced to VSS=0V, TA=0 to 70°C)
Parameter
Supply Voltage (for device with a nominal VCC of 2.5V)I/O Supply VoltageI/O Reference VoltageI/OTermination VoltageInput Logic High VoltageInput Logic Low Voltage
Input Voltage Level, CK and CK# InputsInput Differential Voltage, CK and CK# InputsV-I Matching: Pullup to Pulldown Current RatioInput leakage currentOutput leakage current
Output High Current(Normal strengh driver); VOUT = VTT = 0.84VOutput High Current(Normal strengh driver); VOUT = VTT = 0.84VOutput High Current(Half strengh driver); VOUT = VTT = 0.45VOutput High Current(Half strengh driver); VOUT = VTT = 0.45V
SymbolVCCVCCQVREFVTTVIHVILVIN(DC)VID(DC)VI(Ratio)IIIOZIOHIOLVOHVOL
Min2.32.30.49*VCCQVREF-0.04VREF + 0.15-0.3-0.30.360.71-2-5-16.816.8-99
Max2.72.70.51*VCCQVREF+0.04VCCQ + 0.3VREF -0.15VCCQ + 0.3VCCQ + 0.61.425
UnitVVVVVVVV-uAuAuAuAuAuA
3412Note
NOTES: 1. VREF is expected to be equal to 0.5*VCCQ of the transmitting device, and to track variations in the dc level of same. Peak-to peak noise on VREF may not exceed +/-2% of the dc
value.
2. VTT is not applied directly to the device. VTT is a system supply for signal termination resistors, is expected to be set equal to VREF, and must track variations in the DC level of
VREF.
3. VID is the magnitude of the difference between the input level on CK and the input level on CK#.4. The ratio of the pullup current to the pulldown current is specifi ed for the same temperature and voltage, over the entire temperature and voltage range, for device drain to source
voltages from 0.25V to 1.0V. For a given output, it represents the maximum difference between pullup and pulldown drivers due to process variation. The full variation in the ratio of the maximum to minimum pullup and pulldown current will not exceed 1/7 for device drain to source voltages from 0.1 to 1.0.
November 2005Rev. 2
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White Electronic DesignsCAPACITANCE
TA = 25°C. f = 1MHz, VCC = 2.5V
Parameter
Input Capacitance (A0-A11)Input Capacitance (RAS#,CAS#,WE#)Input Capacitance (CKE0, CKE1, CKE2)Input Capacitance (CLK0, CLK1, CLK2)Input Capacitance (CS0#, CS1#)Input Capacitance (DMO ~ DM7)Input Capacitance (BA0-BA1)
Data input/output capacitance (DQ0-DQ63)(DQS)Data input/output capacitance (CB0-CB7)
SymbolCIN1CIN2CIN3CIN4CIN5CIN6CIN7COUTCOUT
W3EG6433S-D3
-JD3
PRELIMINARY
Max8181503450128112-
UnitpFpFpFpFpFpFpFpFpF
November 2005Rev. 2
5White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
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White Electronic DesignsIDD SPECIFICATIONS AND TEST CONDITIONS
0°C ≤ TA ≤ 70°C, VCCQ = 2.5V ± 0.2V, VCC = 2.5V ± 0.2V
Includes DDR SDRAM component only
ParameterOperating Current
SymbolIDD0
Conditions
One device bank; Active - Precharge; tRC=tRC (MIN); tCK=tCK (MIN); DQ,DM and DQS inputs changing once per clock cycle; Address and control inputs changing once every two cycles.
One device bank; Active-Read-Precharge Burst = 2; tRC=tRC (MIN); tCK=tCK (MIN); lOUT = 0mA; Address and control inputs changing once per clock cycle.
All device banks idle; Power-down mode; tCK=tCK (MIN); CKE=(low)CS# = High; All device banks idle; tCK=tCK (MIN); CKE = high; Address and other control inputs changing once per clock cycle. VIN = VREF for DQ, DQS and DM.
One device bank active; Power-Down mode; tCK (MIN); CKE=(low)CS# = High; CKE = High; One device bank; Active-Precharge; tRC=tRAS (MAX); tCK=tCK (MIN); DQ, DM and DQS inputs changing twice per clock cycle; Address and other control inputs changing once per clock cycle.Burst = 2; Reads; Continuous burst; One device bank active; Address and control inputs changing once per clock cycle; TCK= TCK (MIN); lOUT = 0mA.
Burst = 2; Writes; Continuous burst; One device bank active; Address and control inputs changing once per clock cycle; tCK=tCK (MIN); DQ,DM and DQS inputs changing once per clock cycle.tRC = tRC (MIN)CKE ≤ 0.2V
Four bank interleaving Reads (BL=4) with auto precharge with tRC=tRC (MIN); tCK=tCK (MIN); Address and control inputs change only during Active Read or Write commands.
DDR333@CL=2.5
Max
680
DDR266@CL=2
Max
640
W3EG6433S-D3
-JD3
PRELIMINARY
DDR266@CL=2/2.5
Max
640
UnitsmA
Operating CurrentIDD1880800800mA
Precharge Power-Down Standby Current
Idle Standby Current
IDD2P242424rnA
IDD2F200180180mA
Active Power-Down Standby Current Active Standby Current
IDD3P IDD3N
240360
200320
200320
mAmA
Operating CurrentIDD4R1,120960960mA
Operating CurrentIDD4W1,1601,0001,000rnA
Auto Refresh Current
Self Refresh CurrentOperating Current
IDD5IDD6IDD7A
1,320162,400
1,240162,000
1,240162,000
mAmAmA
NOTES:
• Module IDD was calculated on the basis of component IDD and can be different measured according to dq hearing cap. • I specifi cation is based on SAMSUNG components. Other DRAM manufactures specifi cation may be different.DD
November 2005Rev. 2
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White Electronic DesignsW3EG6433S-D3
-JD3
PRELIMINARY
DDR SDRAM COMPONENT ELECTRICAL CHARACTERISTICS AND
RECOMMENDED AC OPERATING CONDITIONS
AC CharacteristicsParameterRow cycle timeRefresh row cycle timeRow active timeRAS to CAS delayRow precharge time
Row active to Row active delayWrite recovery time
Last data in to Read commandCol. address to Col. address delayClock cycle timeClock high level widthClock low level width
DQS-out access time from CK/CKOutput data access time from CK/CKData strobe edge to output data edgeRead PreambleRead PostambleCK to valid DQS-inDQS-in setup timeDQS-in hold time
DQS falling edge to CK rising-setup timeDQS falling edge from Ck rising-hold timeDQS-in high level widthDQS-in low level widthDQS-in cycle time
Address and Control Input setup time (fast)Address and Control Input hold time (fast)Address and Control Input setup time (slow)Address and Control Input setup time (slow)Data-out high impedence time from CK/CKData-out high impedence time from CK/CKInput Slew Rate (for input only pins)Input Slew Rate (for I/O pins)
CL=2.0CL=2.5
tCHtCLtDQSCKtACtDQSQtRPREtRPSTtDQSStWPREStWPREtDSStDSHtDQSHtDQSLtDSCtIStIHtIStIHtHZtLZtSL(I)tSL(IO)
-0.70.50.5
SymboltRCtRFCtRAStRCDtRPtRRDtWRtWTDtCCDtCK
Min60724218181215117.560.450.45-0.6-0.7-0.90.40.7500.250.20.20.350.350.90.750.750.80.8
+0.7+0.7
-0.750.50.5
1.112120.550.55+0.6+0.70.451.10.61.2570K335
(DDR333@CL=2.5)
262
(DDR266@CL=2.0)
263
(DDR266@CL=2.0)
265
(DDR266@CL=2.5)
Max
Unitsnsns
120K
nsnsnsnsnstCKtCK
12120.550.55+0.75+0.750.51.10.61.25
nsnstCKtCKnsnsnstCKtCKtCKnstCKtCKtCKtCKtCK
1.1
tCKnsnsnsns
+0.75
nsnsV/nsV/ns
+0.75
i,5.7~9i,5.7~9i,6~9i,6~911312Notes
MaxMin60754515151515117.57.50.450.45-0.75-0.75-0.90.40.7500.250.20.20.350.350.90.90.91.01.0
MaxMin75
MaxMin75
65 65120K
452020151511
12120.550.55+0.75+0.750.51.10.61.25
7.57.50.450.45-0.75-0.75-0.90.40.7500.250.20.20.350.35
1.1
0.90.90.91.01.0
+0.75+0.75
-0.750.50.5
+0.75+0.75
-0.750.50.5
1.112120.550.55+0.75+0.750.51.10.61.25120K
452020151511107.50.450.45-0.75-0.75-0.90.40.7500.250.20.20.350.350.90.90.91.01.0
November 2005Rev. 2
7White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
元器件交易网www.cecb2b.com
White Electronic DesignsW3EG6433S-D3
-JD3
PRELIMINARY
DDR SDRAM COMPONENT ELECTRICAL CHARACTERISTICS AND
RECOMMENDED AC OPERATING CONDITIONS (continued)
AC CharacteristicsParameter
Output Slew Rate (x4,x8)
Output Slew Rate Matching Ratio (rise to fall)
Mode register set cycle timeDQ & DM setup time to DQSDQ & DM hold time to DQSControl & Address input pulse widthDQ & DM input pulse widthPower down exit time
Exit self refresh to non-Read commandExit self refresh to read commandRefreash interval timeOutput DQS valid windowClock half periodData hold skew factorDQS write postamble timeActive to Read with Auto precharge command
Autoprecharge write recovery & Precharge time
SymboltSL(O)tSLMRtMRDtDStDHtIPWtDIPWtRDEXtXSRDtXSRDtREFItQHtQHtQHStWPSTtRAPtXSNR
0.418tWR/tCK + tRP/tCK)tHP-tQHStCLmin or tchminMin1.00.67120.50.452.21.75675200
15.6--
335
(DDR333@CL=2.5)
262
(DDR266@CL=2.0)
263
(DDR266@CL=2.0)
265
(DDR266@CL=2.5)
Max4.51.5
Min1.00.67150.50.52.21.757.575200
Max4.51.5
Min1.00.67150.50.52.21.757.575200
Max4.51.5
Min1.00.67150.50.52.21.757.575200
Max4.51.5
UnitsV/nsnsnsnsnsnsnsnsnstCK
Notes
j, kj, k88
15.6
tHP-tQHStCLmin or tchmin0.420tWR/tCK + tRP/tCK)
--
15.6
tHP-tQHStCLmin or tchmin0.420tWR/tCK + tRP/tCK)
--
15.6
tHP-tQHStCLmin or tchmin
0.75
0.420tWR/tCK + tRP/tCK)
0.6
usnsnsnstCK
41110, 11112
0.550.6
0.750.6
0.750.6
tCK13
November 2005Rev. 2
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White Electronic DesignsNotes
1. tHZ and tLZ transitions occur in the same access time windows as
valid data transitions. These parameters are not referenced to a specifi c voltage level but specify when the device output in no longer driving (HZ), or begins driving (LZ).2.
The maximum limit for this parameter is not a device limit. The device will operate with a greater value for this parameter, but system performance (bus turnaround) will degrade accordingly.The specifi c requirement is that DQS be valid (HIGH, LOW, or at some point on a valid transition) on or before this CK edge. A valid transition is defi ned as monotonic and meeting the input slew rate specifi cations of the device. When no writes were previously in progress on the bus, DQS will be transitioning from High- Z to logic LOW. If a previous write was in progress, DQS could be HIGH, LOW, or transitioning from HIGH to LOW at this time, depending on tDQSS.
A maximum of eight AUTO REFRESH commands can be posted to any given DDR SDRAM device.
For command/address input slew rate ≥ 1.0 V/ns.
For command/address input slew rate ≥ 0.5 V/ns and > 1.0 V/nsFor CK & CK# slew rate ≥ 1.0 V/ns.
These parameters guarantee device timing, but they are not necessarily tested on each device. They may be guaranteed by device design or tester correlation.
9.
W3EG6433S-D3
-JD3
PRELIMINARY
Slew Rate is measured between VOH(ac) and VOL(ac).
10. Min (tCL, tCH) refers to the smaller of the actual clock low time and
the actual clock high time as provided to the device (i.e. this value can be greater than the minimum specifi cation limits for tCL and tCH. For example, tCL and tCH are = 50% of the period, less the half period jitter (tJIT(HP)) of the clock source, and less the half period jitter due to crosstalk (tJIT(crosstalk)) into the clock traces.11. tQH = tHP - tQHS, where:
tHP = minimum half clock period for any given cycle and is defi ned by clock high or clock low tCH, tCL). tQHS accounts for 1) The pulse duration distortion of on-chip clock circuits; and 2) The worst case push-out of DQS on one transition followed by the worst case pull-in of DQ on the next transition, both of which are, separately, due to data pin skew and output pattern effects, and p-channel to n-channel variation of the output drivers.12. tDQSQ
Consists of data pin skew and output pattern effects and p-channel to n-channel variation of the output drivers for any given cycle.13. tDAL = (tWR/tCK) + (tRP/tCK)
For each of the terms above, if not already an integer, round to the next highest integer. Example: For DDR266 at CL=2.5 and tCK=7.5ns tDAL = (15 ns / 7.5 ns) + (20 ns/ 7.5ns) = (2) + (3) tDAL = 5 clocks
3.
4. 5. 6. 7. 8.
November 2005Rev. 2
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White Electronic DesignsORDERING INFORMATION FOR JD3
Part NumberW3EG6433S335JD3W3EG6433S263JD3W3EG6433S263JD3W3EG6433S265JD3
Speed166MHz/333Mb/s133MHz/266Mb/s133MHz/266Mb/s133MHz/266Mb/s
CAS Latency
2.5222.5
tRCD3233
W3EG6433S-D3
-JD3
PRELIMINARY
tRP3233
Height*30.48 (1.20\")30.48 (1.20\")30.48 (1.20\")30.48 (1.20\")
NOTES: • Consult Factory for availability of RoHS compliant products. (G = RoHS Compliant) • V endor specifi c part numbers are used to provide memory components source control. The place holder for this is shown as lower case “x” in the part numbers above and is to
be replaced with the respective vendors code. Consult factory for qualifi ed sourcing options. (M = Micron, S = Samsung & consult factory for others)
• Consult factory for availability of industrial temperature (-40°C to 85°C) option
PACKAGE DIMENSIONS FOR JD3
133.48(5.255\" MAX.)131.34(5.171\")128.95(5.077\")3.99(0.157 (2x))30.48(1.20)MAX3.99(0.157)(MIN)2.54(0.100)17.78(0.700)10.01(0.394)6.35(0.250)64.77(2.550)1.27(0.050 TYP.)6.35(0.250)1.78(0.070)49.53(1.950)2.31(0.091)(2x)3.00(0.118)(4x)1.27 ± 0.10(0.050 ± 0.004)* ALL DIMENSIONS ARE IN MILLIMETERS AND (INCHES)
November 2005Rev. 2
10White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
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White Electronic DesignsORDERING INFORMATION FOR D3
Part NumberW3EG6433S335D3W3EG6433S262D3W3EG6433S263D3W3EG6433S265D3
Speed166MHz/333Mb/s133MHz/266Mb/s133MHz/266Mb/s133MHz/266Mb/s
CAS Latency
2.5222.5
tRCD3233
W3EG6433S-D3
-JD3
PRELIMINARY
tRP3233
Height*30.48 (1.20\")30.48 (1.20\")30.48 (1.20\")30.48 (1.20\")
NOTES: • Consult Factory for availability of RoHS compliant products. (G = RoHS Compliant) • V endor specifi c part numbers are used to provide memory components source control. The place holder for this is shown as lower case “x” in the part numbers above and is to
be replaced with the respective vendors code. Consult factory for qualifi ed sourcing options. (M = Micron, S = Samsung & consult factory for others)
• Consult factory for availability of industrial temperature (-40°C to 85°C) option
PACKAGE DIMENSIONS FOR D3
133.48(5.255\" MAX.)131.34(5.171\")128.95(5.077\")3.99(0.157 (2x))30.48(1.20)MAX3.99(0.157)(MIN)2.54(0.100)17.78(0.700)10.01(0.394)6.35(0.250)64.77(2.550)1.27(0.050 TYP.)6.35(0.250)1.78(0.070)49.53(1.950)2.31(0.091)(2x)3.00(0.118)(4x)1.27 ± 0.10(0.050 ± 0.004)* ALL DIMENSIONS ARE IN MILLIMETERS AND (INCHES)
November 2005Rev. 2
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White Electronic DesignsDocument Title
256MB – 2x16Mx64 DDR SDRAM UNBUFFERED
W3EG6433S-D3
-JD3
PRELIMINARY
Revision HistoryRev #
Rev 1
History
1.1 Created Datasheet
1.2 Added lead-free and RoHS notes1.3 Added AC specs
1.4 Moved from Advanced to Preliminary
Release Date
12-04
Status
Preliminary
Rev 22.1 Added JEDEC standard PCB
2.2 D3 option is \"NOT RECOMMENDED FOR NEW
DESIGNS\"2.3 Added lead-free and RoHS notes2.4 Added source control notes
2.5 Added industrial temperature options
5-05Preliminary
Rev 33.1 Update AC, IDD and cap specs3.2 Add 333MH speed
11-05Preliminary
November 2005Rev. 2
12White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
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