Table 2-7:
LBUS Interface – RX Path Control/Status Signals (Cont’d)Name
I/O
Domain
Description
The signal STAT_RX_PCSL_NUMBER_0[4:0] indicates which PCS lane is received on physical lane 0.There are a total of 20
separate STAT_RX_PCSL_NUMBER[4:0] buses This bus is only valid when the corresponding bit of be
STAT_RX_SYNCED[19:0] is a 1. These outputs are level sensitive.
This signal indicates which PCS lane is received on physical lane 1.
This signal indicates which PCS lane is received on physical lane 2.
This signal indicates which PCS lane is received on physical lane 3.
This signal indicates which PCS lane is received on physical lane 4.
This signal indicates which PCS lane is received on physical lane 5.
This signal indicates which PCS lane is received on physical lane 6.
This signal indicates which PCS lane is received on physical lane 7.
This signal indicates which PCS lane is received on physical lane 8.
This signal indicates which PCS lane is received on physical lane 9.
This signal indicates which PCS lane is received on physical lane 10.
This signal indicates which PCS lane is received on physical lane 11.
This signal indicates which PCS lane is received on physical lane 12.
This signal indicates which PCS lane is received on physical lane 13.
This signal indicates which PCS lane is received on physical lane 14.
This signal indicates which PCS lane is received on physical lane 15.
This signal indicates which PCS lane is received on physical lane 16.
This signal indicates which PCS lane is received on physical lane 17.
STAT_RX_PCSL_NUMBER_0[4:0]ORX_CLK
STAT_RX_PCSL_NUMBER_1[4:0]STAT_RX_PCSL_NUMBER_2[4:0]STAT_RX_PCSL_NUMBER_3[4:0]STAT_RX_PCSL_NUMBER_4[4:0]STAT_RX_PCSL_NUMBER_5[4:0]STAT_RX_PCSL_NUMBER_6[4:0]STAT_RX_PCSL_NUMBER_7[4:0]STAT_RX_PCSL_NUMBER_8[4:0]STAT_RX_PCSL_NUMBER_9[4:0]STAT_RX_PCSL_NUMBER_10[4:0]STAT_RX_PCSL_NUMBER_11[4:0]STAT_RX_PCSL_NUMBER_12[4:0]STAT_RX_PCSL_NUMBER_13[4:0]STAT_RX_PCSL_NUMBER_14[4:0]STAT_RX_PCSL_NUMBER_15[4:0]STAT_RX_PCSL_NUMBER_16[4:0]STAT_RX_PCSL_NUMBER_17[4:0]
OOOOOOOOOOOOOOOOO
RX_CLKRX_CLKRX_CLKRX_CLKRX_CLKRX_CLKRX_CLKRX_CLKRX_CLKRX_CLKRX_CLKRX_CLKRX_CLKRX_CLKRX_CLKRX_CLKRX_CLK
Integrated 100G Ethernet Subsystem v2.6PG165 February 4, 2021
Chapter 2:Product Specification
Table 2-7:
LBUS Interface – RX Path Control/Status Signals (Cont’d)Name
I/O
Domain
Description
BIP8 error indicator for PCS lane 0. A
non-zero value indicates the BIP8 signature byte was in error for the corresponding PCS lane. A non-zero value is pulsed for one clock cycle. This output is pulsed for one clock cycle to indicate an error condition. Pulses can occur in back-to-back cycles.BIP8 error indicator for PCS lane 1.BIP8 error indicator for PCS lane 2.BIP8 error indicator for PCS lane 3.BIP8 error indicator for PCS lane 4.BIP8 error indicator for PCS lane 5.BIP8 error indicator for PCS lane 6.BIP8 error indicator for PCS lane 7.BIP8 error indicator for PCS lane 8.BIP8 error indicator for PCS lane 9.BIP8 error indicator for PCS lane 10.BIP8 error indicator for PCS lane 11.BIP8 error indicator for PCS lane 12.BIP8 error indicator for PCS lane 13.BIP8 error indicator for PCS lane 14.BIP8 error indicator for PCS lane 15.BIP8 error indicator for PCS lane 16.BIP8 error indicator for PCS lane 17.BIP8 error indicator for PCS lane 18.BIP8 error indicator for PCS lane 19.High Bit Error Rate (BER) indicator. When set to 1, the BER is too high as defined by the 802.3. Corresponds to MDIO register bit 3.32.1 as defined in Clause 82.3. This output is level sensitive.
STAT_RX_BIP_ERR_0ORX_CLK
STAT_RX_BIP_ERR_1STAT_RX_BIP_ERR_2STAT_RX_BIP_ERR_3STAT_RX_BIP_ERR_4STAT_RX_BIP_ERR_5STAT_RX_BIP_ERR_6STAT_RX_BIP_ERR_7STAT_RX_BIP_ERR_8STAT_RX_BIP_ERR_9STAT_RX_BIP_ERR_10STAT_RX_BIP_ERR_11STAT_RX_BIP_ERR_12STAT_RX_BIP_ERR_13STAT_RX_BIP_ERR_14STAT_RX_BIP_ERR_15STAT_RX_BIP_ERR_16STAT_RX_BIP_ERR_17STAT_RX_BIP_ERR_18STAT_RX_BIP_ERR_19
OOOOOOOOOOOOOOOOOOO
RX_CLKRX_CLKRX_CLKRX_CLKRX_CLKRX_CLKRX_CLKRX_CLKRX_CLKRX_CLKRX_CLKRX_CLKRX_CLKRX_CLKRX_CLKRX_CLKRX_CLKRX_CLKRX_CLK
STAT_RX_HI_BERORX_CLK
Integrated 100G Ethernet Subsystem v2.6PG165 February 4, 2021
Chapter 2:Product Specification
Table 2-9:Statistics Interface – RX PathName
I/O
OO
Domain
RX_CLKRX_CLK
Description
Increment for the total number of bytes received.
Increment for the total number of packets received.
Increment for the total number of good bytes received. This value is only non-zero when a packet is received completely and contains no errors.
Increment for the total number of good packets received. This value is only non-zero when a packet is received completely and contains no errors.
Increment for packets between 64 and ctl_rx_max_packet_len bytes that have FCS errors.
Increment for good and bad packets received that contain 64 bytes.
Increment for good and bad packets received that contain 65 to 127 bytes.
Increment for good and bad packets received that contain 128 to 255 bytes.
Increment for good and bad packets received that contain 256 to 511 bytes.
Increment for good and bad packets received that contain 512 to 1,023 bytes.
Increment for good and bad packets received that contain 1,024 to 1,518 bytes.
Increment for good and bad packets received that contain 1,519 to 1,522 bytes.
Increment for good and bad packets received that contain 1,523 to 1,548 bytes.
Increment for good and bad packets received that contain 1,549 to 2,047 bytes.
Increment for good and bad packets received that contain 2,048 to 4,095 bytes.
Increment for good and bad packets received that contain 4,096 to 8,191 bytes.
STAT_RX_TOTAL_BYTES[7:0]STAT_RX_TOTAL_PACKETS[3:0]
STAT_RX_TOTAL_GOOD_BYTES[13:0]ORX_CLK
STAT_RX_TOTAL_GOOD_PACKETSORX_CLK
STAT_RX_PACKET_BAD_FCSORX_CLK
STAT_RX_PACKET_64_BYTESORX_CLK
STAT_RX_PACKET_65_127_BYTESORX_CLK
STAT_RX_PACKET_128_255_BYTESSTAT_RX_PACKET_256_511_BYTESSTAT_RX_PACKET_512_1023_BYTESSTAT_RX_PACKET_1024_1518_BYTESSTAT_RX_PACKET_1519_1522_BYTESSTAT_RX_PACKET_1523_1548_BYTESSTAT_RX_PACKET_1549_2047_BYTESSTAT_RX_PACKET_2048_4095_BYTESSTAT_RX_PACKET_4096_8191_BYTES
OOOOOOOOO
RX_CLKRX_CLKRX_CLKRX_CLKRX_CLKRX_CLKRX_CLKRX_CLKRX_CLK
Integrated 100G Ethernet Subsystem v2.6PG165 February 4, 2021
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