4250资料

2023-07-04 来源：意榕旅游网

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To all our customersRegarding the change of names mentioned in the document, such as Mitsubishi Electric and Mitsubishi XX, to Renesas Technology Corp.The semiconductor operations of Hitachi and Mitsubishi Electric were transferred to Renesas Technology Corporation on April 1st 2003. These operations include microcomputer, logic, analog and discrete devices, and memory chips other than DRAMs (flash memory, SRAMs etc.) Accordingly, although Mitsubishi Electric, Mitsubishi Electric Corporation, Mitsubishi Semiconductors, and other Mitsubishi brand names are mentioned in the document, these names have in fact all been changed to Renesas Technology Corp. Thank you for your understanding. Except for our corporate trademark, logo and corporate statement, no changes whatsoever have been made to the contents of the document, and these changes do not constitute any alteration to the contents of the document itself.Note : Mitsubishi Electric will continue the business operations of high frequency & optical devices and power devices.Renesas Technology Corp.Customer Support Dept.April 1, 2003元器件交易网www.cecb2b.com

MITSUBISHI MICROCOMPUTERS

4250 Group

SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER

DESCRIPTION

The 4250 Group is a 4-bit single-chip microcomputer designedwith CMOS technology. Its CPU is that of the 720 series using asimple instruction set. The computer is equipped with one 8-bittimer which has a reload register and the interrupt function.The various microcomputers in the 4250 Group include variationsof the built-in memory type as shown in the table below.

•Timer

Timer 1................................8-bit timer with a reload register•Interrupt...................................................................2 sources•CR oscillation circuit (Capacitor and Resistor connectedexternally)

•Logic operation instruction•RAM back-up function

•Key-on wakeup function (ports G and S, INT pin)

FEATURES

•Minimum instruction execution time.............................1.0 µs(at 4.0 MHz system clock frequency, VDD=4.5 V to 5.5 V)•Supply voltage

4.5 V to 5.5 V (at 4.0 MHz system clock frequency)2.5 V to 5.5 V (at 1.0 MHz system clock frequency)2.2 V to 5.5 V (at 1.0 MHz system clock frequency:only for Mask ROM version)

ROM (PROM) size(✕ 9 bits)2048 words2048 wordsAPPLICATION

Electric household appliances, consumer electronics products(mouse, etc.)

ProductM34250M2-XXXFPM34250E2-XXXFP *RAM size(✕ 4 bits)64 words64 wordsPackage20P2N-A20P2N-AROM typeMask ROMOne Time PROM*: Shipped after writing (shipped in blank: M34250E2FP)PIN CONFIGURATION (TOP VIEW)M34250M2-XXXFPVDDVSSXINXOUTCNVSSRESETF0F1G0/INTG1/TOUT122019D0D1D2/CD3/KS0S1S2S3G3G2M34250M2-XXXFP3456789101817161514131211Outline 20P2N-A元器件交易网www.cecb2b.com

BLOCK DIAGRAM2444I/O portPort FPort GPort DPort SInternal peripheral functionsTimerXIN -XOUTSystem clock generating circuitTimer 1 (8 bits)MemoryROM(Note)(2048 words ! 9 bits)720 seriesCPU coreALU (4 bits)Register A (4 bits)Register B (4 bits)Register E (8 bits)Register D (3 bits)Stack register (SK) (4 levels)Interrupt stack register (SDP) (1 level)RAM(64 words ! 4 bits)MITSUBISHI MICROCOMPUTERS

4250 Group

SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER

Note: PROM 2048 words ! 9 bits元器件交易网www.cecb2b.com

MITSUBISHI MICROCOMPUTERS

4250 Group

SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER

PERFORMANCE OVERVIEW

Parameter

Number of basic instructions

Function

Minimum instruction execution time1.0 µs (at 4.0 MHz system clock frequency) (Refer to the electrical characteristics because

the minimum instruction execution time depends on the supply voltage.)

M34250M2/2048 words ! 9 bitsMemory sizesROM

RAM

Input/Output

ports

D0–D3S0–S3CKF0, F1G0–G3INTTOUT

TimerInterrupt

Timer 1

SourcesNesting

Oscillation circuit

E2I/OI/OI/OI/OI/OI/OInputOutput

64 words ! 4 bits

Four independent I/O ports; ports D2 and D3 are also used as ports C and K, respectively.4-bit I/O port

1-bit I/O port; port C is also used as port D2.1-bit I/O port; port K is also used as port D3.2-bit I/O port

4-bit I/O port; ports G0 and G1 are also used as pins INT and TOUT.Interrupt input; INT pin is also used as port G0.Timer output; TOUT pin is also used as port G1.8-bit timer with a reload register

2 (one for external and one for timer)1 level

CR oscillation circuit (a capacitor and a resistor connected externally)Frequency error: ±17 %

(VDD = 5 V ± 10 %, VDD = 3 V ± 10 %, the error of the external capacitor and resistor excluded)

Subroutine nestingDevice structurePackage

Operating temperature rangeSupply voltagePower

Active mode

4 levels

CMOS silicon gate

20-pin plastic molded SOP (20P2N-A)–20 °C to 85 °C

2.2 V to 5.5 V (Refer to the electrical characteristics because the supply voltage depends onthe system clock frequency.)1.5 mA

(at 4.0 MHz system clock frequency, VDD = 5 V, output transistors in the cut-off state)dissipation

(typical value)RAM back-up mode0.1 µA (at room temperature, VDD = 5 V, output transistors in the cut-off state)

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MITSUBISHI MICROCOMPUTERS

4250 Group

SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER

PIN DESCRIPTION

PinVDDVSSCNVSSRESETName

Power supplyGroundCNVSS

Reset input

System clock inputSystem clock outputI/O port FI/O port GInput/Output———InputInputOutputI/OI/OConnected to a plus power supply.Connected to a 0 V power supply.

Function

Connect CNVSS to VSS and apply “L” (0V) to CNVSS certainly.

Reset pulse input pin

I/O pins of the system clock generating circuit. Connect pins XIN and XOUT directly.Then, pull up XIN pin through a resistor and pull down XOUT pin through a capacitor.2-bit I/O port; for input use, set the latch of the specified bit to “1.” The outputstructure is N-channel open-drain.

4-bit I/O port. For input use, set the latch of the specified bit to “1.” The outputstructure is N-channel open-drain. Every pin of the ports has a key-on wakeupfunction and a pull-up function. Both functions can be switched by software.Ports G0 and G1 are also used as pins INT and TOUT, respectively.

XINXOUTF0, F1G0–G3

S0–S3I/O port SI/O

4-bit I/O port. For input use, set the latch of the specified bit to “1.” The outputstructure is N-channel open-drain. Every pin of the ports has a key-on wakeupfunction which can be switched by software. Also, it is used to perform the logicoperation using register A.

Each pin of port D has an independent 1-bit wide I/O function. For input use, setthe latch of the specified bit to “1.” The output structure is N-channel open-drain.Ports D2 and D3 are also used as ports C and K, respectively.

1-bit I/O port. For input use, set the latch of the specified bit to “1.” The outputstructure is N-channel open-drain. Port C has a pull-up function which can beswitched by software. It is also used as port D2.

1-bit I/O port. For input use, set the latch of the specified bit to “1.” The outputstructure is N-channel open-drain. Port K has a pull-up function which can beswitched by software. It is also used as port D3.

TOUT pin has the function to output the timer 1 underflow signal divided by 2. It isalso used as port G1.

INT pin accepts an external interrupt. It also accepts the input signal to return thesystem from the RAM back-up state. It is also used as port G0.

D0–D3I/O port DI/O

CI/O port CI/O

KI/O port KI/O

TOUTINT

Timer outputInterrupt input

OutputInput

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MITSUBISHI MICROCOMPUTERS

4250 Group

SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER

MULTIFUNCTION

G0G1D2

INTTOUTC

Multifunction

INT (Note 2)TOUT (Note 2)C (Note 2)

G0G1D2D3

MultifunctionD3KK (Note 2)Notes 1: Pins except above have just single function.

2: The I/O of ports D2, D3 and G0, and the input of port G1 can be used even when ports C and K and pins INT and TOUT areselected.

CONNECTIONS OF UNUSED PINS

F0, F1

G0/INT, G1/TOUTG2, G3S0–S3

Connection

Connect to VSS pin.

Open or connect to VSS pin. (Note 1)Connect to VSS pin. (Note 2)

D0, D1D2/C, D3/K

Connection

Connect to VSS pin.

Open or connect to VSS pin. (Note 3)

Notes 1: When pins G0/INT, G1/TOUT, G2 and G3 are connected to VSS pin, turn off their pull-up transistors (Pull-up control register

PU0=“!02”) and also invalidate the key-on wakeup functions of pins G1/TOUT, G2 and G3 (Key-on wakeup contorl registerK0=“!!0!2”) by software. When the POF instruction is executed while these pins are connected to VSS and the key-onwakeup functions are left valid, the system returns from RAM back-up state by recognizing the return condition immediatelyafter going into the RAM back-up state. When these pins are open, turn on their pull-up transistors (Pull-up control registerPU0=“!12”) by software.

2: When ports S0–S3 are connected to VSS pin, invalidate the key-on wakeup functions (Key-on wakeup contorl registerK0=“!!!02”) by software. When the POF instruction is executed while these pins are connected to VSS and the key-onwakeup functions are left valid, the system returns from RAM back-up state by recognizing the return condition immediatelyafter going into the RAM back-up state.3: When ports D2/C and D3/K are connected to VSS pin, turn off their pull-up transistors (register PU0=“0!2”) by software.When these pins are open, turn on their pull-up transistors (register PU0=“1!2”) by software.(Note when connecting to VSS and VDD)

•Connect the unused pins to VSS or VDD at the shortest distance and use the thick wire against noise.

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MITSUBISHI MICROCOMPUTERS

4250 Group

SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER

PORT FUNCTION

PortPort D

D0, D1D2/CD3/K

Input/OutputI/O(4)

Output structureN-channel open-drain

Controlbits1

Control instructionsSDRDSZDCLDSCPRCPSNZCPOKA

Port S

S0–S3

I/O(4)

N-channel open-drain

IAKOSAIASLGOP

Port G

G0/INT

I/O(4)

N-channel open-drain

OGAIAG

PU0, K0K0LO

Logic operation function(programmable)

Key-on wakeup functions(programmable)

Pull-up functions

Key-on wakeup functions(only pull-up function is

G1/TOUTG2, G3

Port F

F0, F1

I/O(2)

N-channel open-drain

OFAIAF

PU0, K0V1PU0, K0

programmable)Pull-up functions(programmable)

Key-on wakeup functions(programmable)

ControlregistersPU0

Remark

Pull-up function(programmable)

DEFINITION OF CLOCK AND CYCLE

•System clock

This is the source clock input to the XIN pin. Connect pins XINand XOUT directly. Then, pull up XIN pin through a resistor andpull down XOUT pin through a capacitor.•Instruction clock

The instruction clock is a signal derived by dividing the systemclock by 4, and is the basic clock for controlling this product.•Machine cycle

One machine cycle is the time required to execute the minimuminstruction (one-cycle instruction). The machine cycle isequivalent to the instruction clock cycle.

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MITSUBISHI MICROCOMPUTERS

4250 Group

SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER

I/O PORT

(1) Port D (D0–D3)

Each pin of port D has an independent 1-bit wide I/O function.Each pin has an output latch. For input/output of ports D0–D3,select one of port D with the register Y of data pointer first. Forinput use, set the latch of the specified bit to “1.” All port Doutput latches can be set to “1” with the CLD instruction. Theoutput structure is the N-channel open-drain. Ports D2 and D3are also used as ports C and K, respectively. Accordingly,when port D2/C is used as port D2, set the port C output latchto “1.” When port D3/K is used as port D3, set the port K outputlatch to “1.”(2) Port C

1-bit I/O port.

Port C output latch can be set to “1” with the SCP instruction.Port C output latch can be cleared to “0” with the RCPinstruction. Port C input level can be examined by executingthe skip (SNZCP) instruction. For input use, set the latch ofthe specified bit to “1.” The output structure is the N-channelopen-drain. The pull-up transistor of port C is turned on whenthe bit 1 of register PU0 is set to “1” by software. Port C is alsoused as port D2. Accordingly, when port D2/C is used as portC, set the port D2 output latch to “1.”Pull-up control register

Pull-up control register PU0

PU01PU00

Ports C and K

pull-up transistor control bitPorts G0–G3

0101

(3) Port K

1-bit I/O port.

For input use, set the latch of the specified bit to “1.” Theoutput structure is the N-channel open-drain. The pull-uptransistor of port K is turned on when the bit 1 of register PU0is set to “1” by software. Port K is also used as port D3.Accordingly, when port D3/K is used as port K, set the port D3output latch to “1.”(4) Port G (G0–G3)

4-bit I/O port.

For input use, set the latch of the specified bit to “1.” Theoutput structure is the N-channel open-drain. The pull-uptransistor of port G is turned on when the bit 0 of register PU0is set to “1” by software. Ports G0 and G1 are also used as INTpin and TOUT pin, respectively.

at reset : 002at RAM back-up : state retainedW

Pull-up transistor OFFPull-up transistor ONPull-up transistor OFFPull-up transistor ON

pull-up transistor control bit

Note: “W” represents write enabled.

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MITSUBISHI MICROCOMPUTERS

4250 Group

SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER

(5) Port F (F0, F1)

2-bit I/O port.

For input use, set the latch of the specified bit to “1.” The outputstructure is the N-channel open-drain.(6) Port S (S0–S3)

4-bit I/O port.

Port S has the logic operation (LGOP) function. For input (logicoperation included) use, set the latch of the specified bit to“1.” The output structure is the N-channel open-drain. Whenperforming the logic operation, select the logic operationfunction with the logic operation selection register LO. Set thecontents of register LO through register A with the TLOAinstruction.

When the LGOP instruction is executed, the logic operationselected with the register LO is performed between thecontents of register A and the contents of port S, and its resultis stored in register A.Logic operation selection register

Logic operation selection register LOLO1

Logic operation function selection bits

LO0

Note: “W” represents write enabled.

at reset : 002

LO1LO0

0XOR operation0

1OR operation011

0AND operation1Not available

at RAM back-up : 002Functions

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MITSUBISHI MICROCOMPUTERS

4250 Group

SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER

PORT BLOCK DIAGRAMSRegister YDecoderCLDinstructionSkip decision(SZD instruction)SD instructionRD instructionSRQ(Note 1)D0, D1IAF instructionRegister AAjPull-up transistor(Note 3)F0, F1DQOFAinstructionT(Note 1)Register YDecoderCLDinstructionPU01Skip decision(SNZCP instruction)Skip decision(SZD instruction)(Note 1)SD instructionRD instructionSCP instructionRCP instructionSRQSRQD2/CKey-on wakeupinputK00LO RegisterLGOP instructionLogic operator(Note 2)AiIAS instructionPull-up transistorRegister AAiRegister YDecoderCLDinstructionSD instructionRD instructionA0OKA instructionSRQDTQNotes 1:S0–S3DQOSA instructionT(Note 1)PU01IAK instructionRegister ASkip decision(SZD instruction)(Note 1)(Note 2)D3/KThis symbol representsa parasitic diode.Applied potential to ports D0, D1, F0, F1, S0–S3 must be 7V or less.Applied potential to ports D2, D3 must be VDD or less.2:i represents 0, 1, 2 or 3.3:j represents 0 or 1.9

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MITSUBISHI MICROCOMPUTERS

4250 Group

SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER

PORT BLOCK DIAGRAMS (CONTINUED)K020External interruptKey-on wakeup inputEXF0One-sided edge detection circuitPull-up transistorRising(Note 1)1FallingPU00IAG instructionG0/INTRegister AA0OGA instructionDQTPull-up transistorK01Key-on wakeupinputIAG instructionRegister ATimer 1 underflow signal outputA1OGA instructionDQT1/210(Note 1)PU00G1/TOUTV13Pull-up transistorK01Key-on wakeupinputIAG instructionRegister AG2, G3(Note 1)PU00(Note 2)AkDQTOGA instructionNotes 1:This symbol represents a parasitic diode.Applied potential to ports G0–G3 must be VDD or less.2:k represents 2 or 3.10

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MITSUBISHI MICROCOMPUTERS

4250 Group

SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER

FUNCTION BLOCK OPERATIONSCPU

(1) Arithmetic logic unit (ALU)

The arithmetic logic unit ALU performs 4-bit arithmetic suchas 4-bit data addition, comparison, and bit manipulation.(2) Register A and carry flag

Carry flag CY is a 1-bit flag that is set to “1” when there is acarry with the AMC instruction (Figure 1).

It is unchanged with both A n instruction and AM instruction.The value of A0 is stored in carry flag CY with the RARinstruction (Figure 2).

Carry flag CY can be set to “1” with the SC instruction andcleared to “0” with the RC instruction.(3) Registers B and E

Register B is a 4-bit register used for temporary storage of 4-bit data, and for 8-bit data transfer together with register A.Register E is an 8-bit register. It can be used for 8-bit datatransfer with register B used as the high-order 4 bits andregister A as the low-order 4 bits (Figure 3).(4) Register D

It is used to store a 7-bit ROM address together with registerA and is used as a pointer within the specified page when theTABP p, BLA p, or BMLA p instruction is executed (Figure 4).

(CY)(M(DP))Addition(A)Fig. 1 AMC instruction execution exampleALUSC instructionRC instructionCYA3A2A1A0RAR instructionA0CYA3A2A1Fig. 2 RAR instruction execution exampleRegister BTAB instructionRegister AB3B2B1B0A3A2A1A0TEAB instructionRegister EE7E6E5E4E3E2E1E0TABE instructionB3B2B1B0Register BA3A2A1A0TBA instructionRegister AFig. 3 Registers A, B and register EROMTABP p instructionSpecifying addressPCLDR2DR1DR0A3A2A1A0Middle-order 4 bitsRegister B (4)Immediate field The contents of The contents of value pregister Dregister AFig. 4 TABP p instruction execution example840PCHp3p2p1p0Low-order 4 bitsRegister A (4)11

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MITSUBISHI MICROCOMPUTERS

4250 Group

SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER

(5) Stack registers (SKs) and stack pointer (SP)

Stack registers (SKs) are used to temporarily store the contentsof program counter (PC) just before branching until returningto the original routine when;

• branching to an interrupt service routine (referred to as aninterrupt service routine),

• performing a subroutine call, or

• executing the table reference instruction (TABP p).

Stack registers (SKs) are four identical registers, so thatsubroutines can be nested up to 4 levels. However, one ofstack registers is used respectively when using an interruptservice routine and when executing a table referenceinstruction. Accordingly, be careful not to over the stack whenperforming these operations together. The contents of registersSKs are destroyed when 4 levels are exceeded.

The register SK nesting level is pointed automatically by 2-bitstack pointer (SP).

Figure 5 shows the stack registers (SKs) structure.

Figure 6 shows the example of operation at subroutine call.(6) Interrupt stack register (SDP)

Interrupt stack register (SDP) is a 1-stage register. When aninterrupt occurs, this register (SDP) is used to temporarily storethe contents of data pointer, carry flag and skip flag just beforean interrupt until returning to the original routine.

Unlike the stack registers (SKs), this register (SDP) is not usedwhen executing the subroutine call instruction and the tablereference instruction.(7) Skip flag

Skip flag controls skip decision for the conditional skipinstructions and continuous described skip instructions. Whenan interrupt occurs, the contents of skip flag is storedautomatically in the interrupt stack register (SDP) and the skipcondition is retained.

Program counter (PC)Executing BM instructionSK0SK1SK2SK3Executing RTinstruction(SP) = 0(SP) = 1(SP) = 2(SP) = 3Stack pointer (SP) points “3” at reset or returning from RAM back-up mode. It points “0” by executing the first BM instruction, and the contents of program counter is stored in SK0.When the BM instruction is executed after four stack registers are used ((SP) = 3), (SP) = 0 and the contents of SK0 is destroyed. Fig. 5Stack registers (SKs) structure (SP) 0(SK0) 000116 (PC) SUB1Main programAddress000016 NOP000116 BM SUB1000216 NOPSubroutineSUB1 :NOP···RT(PC) (SK0)(SP) 3Note:Returning to the BM instruction execution address with the RT instruction, and the BM instruction is equivalent to the NOP instruction.Fig. 6Example of operation at subroutine call12

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MITSUBISHI MICROCOMPUTERS

4250 Group

SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER

(8) Program counter (PC)

Program counter (PC) is used to specify a ROM address (pageand address). It determines a sequence in which instructionsstored in ROM are read. It is a binary counter that incrementsthe number of instruction bytes each time an instruction isexecuted. However, the value changes to a specified addresswhen branch instructions, subroutine call instructions, returninstructions, or the table reference instruction (TABP p) isexecuted.

Program counter consists of PCH (most significant bit to bit 7)which specifies to a ROM page and PCL (bits 6 to 0) whichspecifies an address within a page. After it reaches the lastaddress (address 127) of a page, it specifies address 0 of thenext page (Figure 7).

Make sure that the PCH does not exceed after the last page ofthe built-in ROM.(9) Data pointer (DP)

Data pointer (DP) is used to specify a RAM address andconsists of registers X and Y. Register X specifies a file andregister Y specifies a RAM digit (Figure 8).

Register Y is also used to specify the port D bit position.When using port D, set the port D bit position to register Ycertainly and execute the SD, RD, or SZD instruction (Figure9).

Program counter (PC)p3p2p1p0PCHSpecifying pagea6a5a4a3a2a1a0PCLSpecifying addressFig. 7 Program counter (PC) structureData pointer (DP)X1X0Y3Y2Y1Y0Register Y (4)Register X (2)Specifying RAM digitSpecifying RAM fileFig. 8 Data pointer (DP) structureSpecifying bit positionSetD3D2D1D000101Port D output latchRegister Y (4)Fig. 9 SD instruction execution example13

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MITSUBISHI MICROCOMPUTERS

4250 Group

SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER

PROGRAM MEMORY (ROM)

The program memory is a mask ROM. 1 word of ROM iscomposed of 9 bits. ROM is separated every 128 words by theunit of page (addresses 0 to 127). Table 1 shows the ROM sizeand pages. Figure 10 shows the ROM map of M34250M2.Table 1 ROM size and pagesProductM34250M2M34250E2

ROM size (! 9 bits)

2048 words

Pages16 (0 to 15)

876000016007F1600801600FF16010016017F16018016543210Page 0Interrupt address pageSubroutine special pagePage 1Page 2Page 3A part of page 1 (addresses 008016 to 00FF16) is reserved forinterrupt addresses (Figure 11). When an interrupt occurs, theaddress (interrupt address) corresponding to each interrupt isset in the program counter, and the instruction at the interruptaddress is executed. When using an interrupt service routine,write the instruction generating the branch to that routine at aninterrupt address.

Page 2 (addresses 010016 to 017F16) is the special page forsubroutine calls. Subroutines written in this page can be calledfrom any page with the 1-word instruction (BM). Subroutinesextending from page 2 to another page can also be called withthe BM instruction when it starts on page 2.

ROM pattern (bits 7 to 0) of all addresses can be used as dataareas with the TABP p instruction.

07FF16Fig. 10 ROM map of M34250M2Page 1500801600821600FF16876543210External interrupt addressTimer 1 interrupt addressDATA MEMORY (RAM)

1 word of RAM is composed of 4 bits, but 1-bit manipulation(with the SB j, RB j, and SZB j instructions) is enabled for theentire memory area. A RAM address is specified by a datapointer. The data pointer consists of registers X and Y. Set avalue to the data pointer certainly when executing an instructionto access RAM.

Table 2 shows the RAM size. Figure 12 shows the RAM map.Table 2 RAM size

Product

M34250M2M34250E2

Fig. 11 Page 1 (addresses 008016 to 00FF16) structureRAM 64 words ! 4 bits (256 bits)Register X0123RAM size

64 words ! 4 bits (256 bits)

012345678910111213141564 wordsFig. 12 RAM map14

MITSUBISHI MICROCOMPUTERS

4250 Group

SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER

INTERRUPT FUNCTION

The interrupt type is a vectored interrupt branching to anindividual address (interrupt address) according to each in-terrupt source. An interrupt occurs when the following 3conditions are satisfied.

•An interrupt activated condition is satisfied(request flag = “1”)

•Interrupt enable bit = “1”

(interrupt request occurrence enabled)

•Interrupt enable flag (INTE) = “1” (interrupt enabled)Table 3 shows interrupt sources. (Refer to each interruptrequest flag for details of activated conditions.)

(1) Interrupt enable flag (INTE)

The interrupt enable flag (INTE) controls whether theevery interrupt enable/disable. Interrupts are enabledwhen INTE flag is set to “1” with the EI instruction anddisabled when INTE flag is cleared to “0” with the DIinstruction. When any interrupt occurs, the INTE flag isautomatically cleared to “0,” so that other interruptsare disabled until the EI instruction is executed.(2) Interrupt enable bit (V10, V11)

Use an interrupt enable bit of interrupt control registerV1 to select the corresponding interrupt or skip instruc-tion.

Table 4 shows the interrupt request flag, interrupt en-able bit and skip instruction.

Table 5 shows the interrupt enable bit function.(3) Interrupt request flag

When the activated condition for each interrupt is sat-isfied, the corresponding interrupt request flag is set to“1.” Each interrupt request flag is cleared to “0” wheneither;

•an interrupt occurs, or

•the next instruction is skipped with a skip instruc-tion.

Each interrupt request flag is set when the activatedcondition is satisfied even if the interrupt is disabledby the INTE flag or its interrupt enable bit. Once set,the interrupt request flag retains set until a clear con-dition is satisfied.

Accordingly, an interrupt occurs when the interrupt dis-able state is released while the interrupt request flagis set.

If more than one interrupt request flag is set when theinterrupt disable state is released, the interrupt prioritylevel is as follows shown in Table 3.

Table 3 Interrupt sourcesPriority

Activated conditionInterrupt name

level

Interruptaddress

External interruptLevel change of INTAddress 0

in page 1pin

Address 2Timer 1 interruptTimer 1 underflow

in page 1

Table 4 Interrupt request flag, interrupt enable bit and

skip instruction

Interrupt nameRequest flagEnable bitSkip instruction

EXF0V10SNZ0External interruptTimer 1 interrupt

T1F

V11

SNZ1

Table 5 Interrupt enable bit functionOccurrence of

Interrupt enable bitinterrupt request

Enabled1

Disabled

Skip instruction

Invalid

Valid

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MITSUBISHI MICROCOMPUTERS

4250 Group

SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER

(4) Internal state during an interrupt

The internal state of the microcomputer during an in-terrupt is as follows (Figure 14).•Program counter (PC)

An interrupt address is set in program counter. Theaddress to be executed when returning to the mainroutine is automatically stored in the stack register(SK).

•Interrupt enable flag (INTE)

INTE flag is cleared to “0” so that interrupts are disa-bled.

•Interrupt request flag

Only the request flag for the current interrupt sourceis cleared to “0.”

•Data pointer, carry flag and skip flag

The contents of these pointer and flags are storedautomatically in the interrupt stack register (SDP).(5) Interrupt processing

When an interrupt occurs, a program at an interruptaddress is executed after branching a data store se-quence to stack register. Write the branch instructionto an interrupt service routine at an interrupt address.Use the RTI instruction to return to main routine.Interrupt enabled by executing the EI instruction is per-formed after executing 1 instruction (just after the nextinstruction is executed). Accordingly, when the EI in-struction is executed just before the RTI instruction,interrupts are enabled after returning the main routine.(Refer to Figure 13)

•Program counter (PC)...........Each interrupt address•Stack register (SK)The address of main routine tobe executed when returning•Interrupt enable flag (INTE)......0 (Interrupt disabled)• Interrupt request flag (only the flag for the current interruptsource)......................................................................0•Data pointer, carry flag, skip flag.........Stored in the interrupt stack register (SDP) automaticallyFig. 14 Internal state when interrupt occursINT pin(L→H or H→L input)Timer 1 underflowEXF0V10Address 0 in page 1Address 2 in page 1EnableflagT1FRequest flag(state retained)V11EnablebitActivated conditionFig. 15 Interrupt system diagramMain routineInterrupt service routineInterrupt occursInterrupt is enabledEIRTI: Interrupt enabled state: Interrupt disabled stateFig. 13 Program example of interrupt processing16

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(6) Control register related to interrupt•Timer control register V1

Interrupt enable bits of external and timer 1 are assignedto register V1. Set the contents of this register throughregister A with the TV1A instruction. The TAV1 instructioncan be used to transfer the contents of register V1 to registerA.Table 6 Control register related to interrupt

Timer control register V1

V13V12V11V10

G1/TOUT pin function selection bitPrescaler/timer 1 operation start bitTimer 1 interrupt enable bitExternal interrupt enable bit

01010101

at reset : 00002Port G1 (I/O)

TOUT pin (output)/port G1(input)

Prescaler stop (initial state) / timer 1 stop (state retained)Prescaler / timer 1 operation

Interrupt disabled (SNZ1 instruction is valid)Interrupt enabled (SNZ1 instruction is invalid)Interrupt disabled (SNZ0 instruction is valid)Interrupt enabled (SNZ0 instruction is invalid)

at RAM back-up : 00002

R/W

Note: “R” represents read enabled, and “W” represents write enabled.(7) Interrupt sequence

Interrupts occur only when the respective INTE flag, interruptenable bits (V10, V11), and interrupt request flags (EXF0, T1F)are “1.” The interrupt actually occurs 2 to 3 machine cyclesafter the cycle in which all three conditions are satisfied. The

interrupt occurs after 3 machine cycles only when the threeinterrupt conditions are satisfied on execution of other thanone-cycle instructions (Refer to Figure 16).

q When an interrupt request flag is set after its interrupt is enabled1 machine cycleT1T2T3T4T1T2T3T4T1T2T3T4T1T2T3T4f (XIN)EI instruction execution cycleInterrupt enabled state.T1T2T3T4Interrupt enable flag (INTE)Interrupt disabled state.G0/INT pinExternal interruptEXF0 flagInterrupt activated condition is satisfied.Timer 1 interruptRetaining level for 5 cycles or more of f(XIN) is necessary.T1F flagFlag cleared2 to 3 machine cycles(Notes 1, 2)Software starts fromthe interrupt address.Notes 1:The address is stacked to the last cycle.2:This interval of cycles depends on the executed instruction at the time when each interrupt activated condition is satisfied.Fig. 16 Interrupt sequence17

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EXTERNAL INTERRUPTS

The 4250 Group has an external interrupt. An external interruptrequest occurs when a valid waveform is input to an interruptinput pin (edge detection).

The external interrupt can be controlled with the key-on wakeupcontrol register K0.

Table 7 External interrupt activated condition

Name

External interrupt

Input pinG0/INT

Valid waveform

Falling waveform (“H”→“L”)Rising waveform (“L”→“H”)

Valid waveform selection bit(K02)

K020External interruptKey-on wakeup inputEXF0One-sided edge detection circuitPull-up transistorRising(Note)1FallingPU00IAG instructionG0/INT pinRegister AA0OGA instructionDQTNote:This symbol represents a parasitic diode.Applied potential to port G0 must be VDD or less.Fig. 17 External interrupt circuit structure

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(1) External interrupt request flag (EXF0)

External interrupt request flag (EXF0) is set to “1” when a validwaveform is input to G0/INT pin.

The valid waveforms causing the interrupt must be retainedat their level for 5 cycles or more of f(XIN) (Refer to Figure16).

The state of EXF0 flag can be examined with the skipinstruction (SNZ0). Use the timer control register V1 to selectthe interrupt or the skip instruction. The EXF0 flag is clearedto “0” when an interrupt occurs or when the next instruction isskipped with the skip instruction.•External interrupt activated condition

External interrupt activated condition is satisfied when avalid waveform is input to G0/INT pin.

The valid waveform can be selected from rising waveformor falling waveform. An example of how to use the externalinterrupt is as follows.󰃀Select the valid waveform with the bit 2 of register K0.󰃁Clear the EXF0 flag to “0” with the SNZ0 instruction.

󰃂Set the NOP instruction for the case when a skip isperformed with the SNZ0 instruction.

󰃃Set both the external interrupt enable bit (V10) and the INTEflag to “1.”The external interrupt is now enabled. Now when a validwaveform is input to the G0/INT pin, the EXF0 flag is set to “1”and the external interrupt occurs.

Table 8 Control register related to external interrupt

Key-on wakeup control register K0K03

Prescaler dividing ratio selection bitInterrupt valid waveform for INT pin/

key-on wakeup valid waveform selectionbit (Note 2)

K01K00

Ports G1–G3 key-on wakeup control bitPorts S0–S3 key-on wakeup control bit

01010101

(2) Control register related to external interrupt•Key-on wakeup control register K0

Register K0 controls the valid waveform for the externalinterrupt and key-on wakeup function. Set the contents ofthis register through register A with the TK0A instruction.The TAK0 instruction can be used to transfer the contentsof register K0 to register A.

at reset : 00002at RAM back-up : state retainedR/W

Instruction clock divided by 4Instruction clock divided by 512Rising waveform (“L” → “H”)Falling waveform (“H” → “L”)

Key-on wakeup not used

Key-on wakeup used (“L” level recognized)Key-on wakeup not used

Key-on wakeup used (“L” level recognized)

K02

Notes 1: “R” represents read enabled, and “W” represents write enabled.

2: Set a value to the bit 2 of register K0, and execute the SNZ0 instruction to clear the EXF0 flag to “0” after executing at leastone instruction. According to the input state of G0/INT pin, the external interrupt request flag (EXF0) may be set to “1” whenthe interrupt valid waveform is changed.

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TIMERS

The 4250 Group has the programmable timer.•Programmable timer

The programmable timer has a reload register and enablesthe frequency dividing ratio to be set. It is decremented from asetting value n. When it underflows (count to n + 1), a timerinterrupt request flag is set to “1,” new data is loaded from thereload register, and count continues (auto-reload function).

FF16n : Counter initial valueCount startsnReloadReloadThe contents of counter1st underflow2nd underflow0016Timen+1 countTimer 1 interrupt request flagAn interrupt occurs or a skip instruction is executed.n+1 countFig. 18 Auto-reload function20

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The 4250 Group timer consists of the following circuits.•Prescaler : frequency divider

•Timer 1 : 8-bit programmable timer with the interrupt functionThese timers can be controlled with the timer control register V1and key-on wakeup control register K0.Each function is described below.Table 9 Function related timers

CircuitPrescalerTimer 1

StructureFrequency divider8-bit programmablebinary down counter

Count source

Instruction clock

Prescaler output (ORCLK)

Frequency

dividing ratio

• Timer 1 count source4, 5121 to 256

• TOUT pin• Timer 1 interrupt

Use of output signal

Controlregister

V1K0V1

PrescalerV1201K031/41/51201V12(Note)0ORCLK1Bit 7Timer 1 (8)Timer 1 underflow signalBit 01/2T1FTimer 1 interruptTimer 1 reload register R 1(8)T1ABinstructionV131TAB1 instructionInstruction clockInternal clock generating circuit (divided by 4)Register B(4)TAB1 instructionRegister A(4)G1 outputG1/TOUTG1 input0Note: Count source is stopped by clearing to “0.”XIN:Data is automatically set from a reload register when timer 1 underflows (auto-reload function).Fig. 19 Timers structure21

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Table 10 Control registers related to timer

Timer control register V1

V13V12V11V10

G1/TOUT pin function selection bitPrescaler/timer 1 operation start bitTimer 1 interrupt enable bitExternal interrupt enable bitKey-on wakeup control register K0K03

Prescaler dividing ratio selection bitInterrupt valid waveform for INT pin/

K02

key-on wakeup valid waveform selectionbit (Note 2)

K01K00

Ports G1–G3 key-on wakeup control bitPorts S0–S3 key-on wakeup control bit

0101010101010101

at reset : 00002

Port G1 (I/O)

TOUT pin (output)/port G1(input)

Prescaler stop (initial state) / timer 1 stop (state retained)Prescaler / timer 1 operation

Interrupt disabled (SNZ1 instruction is valid)Interrupt enabled (SNZ1 instruction is invalid)Interrupt disabled (SNZ0 instruction is valid)Interrupt enabled (SNZ0 instruction is invalid)at reset : 00002

at RAM back-up : state retained

R/W

at RAM back-up : 00002

R/W

Instruction clock divided by 4Instruction clock divided by 512Rising waveform (“L” → “H”)Falling waveform (“H” → “L”)

Key-on wakeup not used

Key-on wakeup used (“L” level recognized)Key-on wakeup not used

Key-on wakeup used (“L” level recognized)

Notes 1: “R” represents read enabled, and “W” represents write enabled.

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(1) Control registers related to timer•Timer control register V1

G1/TOUT pin function selection bit and prescaler/timer 1operation start bit are assigned to register V1. Set thecontents of this register through register A with the TV1Ainstruction. The TAV1 instruction can be used to transferthe contents of register V1 to register A.• Key-on wakeup control register K0

Prescaler dividing ratio selection bit is assigned to registerK0. Set the contents of this register through register A withthe TK0A instruction. The TAK0 instruction can be used totransfer the contents of register K0 to register A.(2) Precautions

Note the following for the use of timers.•Prescaler

Stop the prescaler operation to change its frequency dividingratio.

•Reading the count value

Stop timer 1 counting and then execute the TAB1 instructionto read its data.(3) Prescaler

Prescaler is a frequency divider. Its frequency dividing ratiocan be selected. The count source of prescaler is theinstruction clock.

Use the bit 3 of register K0 to select the prescaler dividingratio and the bit 2 of register V1 to start and stop its operation.Prescaler is initialized, and the output signal (ORCLK) stopswhen the bit 2 of register V1 is cleared to “0.”(4) Timer 1 (interrupt function)

Timer 1 is an 8-bit binary down counter with the timer 1 reloadregister (R1). Data can be set simultaneously in timer 1 andthe reload register (R1) with the T1AB instruction.Timer 1 starts counting after the following process;󰃀 set data in timer 1, and

󰃁 set the bit 2 of register V1 to “1.”

Once count is started, when timer 1 underflows (the next countpulse is input after the contents of timer 1 becomes “0”), thetimer 1 interrupt request flag (T1F) is set to “1,” new data isloaded from reload register R1, and count continues (auto-reload function).

When a value set in reload register R1 is n, timer 1 divides thecount source signal by n + 1 (n = 0 to 255).

Data can be read from timer 1 to registers A and B with theTAB1 instruction. When reading the data, stop the counterand then execute the TAB1 instruction. Timer 1 underflowsignal divided by 2 can be output from G1/TOUT pin.

(5) Timer output pin (G1/TOUT)

Timer output pin (G1/TOUT) has the function to output the timer1 underflow signal divided by 2. The selection of G1/TOUT pinfunction can be controlled with the bit 3 of register V1.(6) Timer interrupt request flag (T1F)

Timer interrupt request flag is set to “1” when the timerunderflows. The state of this flag can be examined with theskip instruction (SNZ1).

Use the register V1 to select an interrupt or a skip instruction.T1F flag is cleared to “0” when an interrupt occurs or when thenext instruction is skipped with a skip instruction.

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RESET FUNCTION

System reset is performed by applying “L” level to RESET pinfor 1 machine cycle or more when the following condition issatisfied;

•the value of supply voltage is the minimum value or more ofthe recommended operating conditions.

Then when “H” level is applied to RESET pin, software startsfrom address 0 in page 0.

f(XIN)RESETSoftware starts(address 0 in page 0)3584 to 3585 machine cyclesThe number of clock cycles depends on the internal state of the microcomputer when reset is performed.Fig. 20 Reset release timingReset input1 machine cycle or more=3584 to 3585 machine cycles0.85VDDRESET0.1VDDSoftware starts(address 0 in page 0)(Note)Note :Keep the value of supply voltage the minimum value or more of the recommended operating conditions.Fig. 21 RESET pin input waveform and reset operation24

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(1) Power-on reset

Reset can be automatically performed at power on (power-onreset) by connecting a resistor, a diode, and a capacitor toRESET pin. Connect RESET pin and the external circuit at theshortest distance.

VDDVDDRESET pin voltageInternal reset signalReset stateRESETpinInternal reset signalThis symbol represents a parasitic diode.Note: Applied potential to RESET pin must be 7 V or less.Fig. 22 Power-on reset circuit example(2) Internal state at reset

Table 11 shows port state at reset, and Figure 23 showsinternal state at reset (they are retained after system is releasedfrom reset).Table 11 Port state at reset

FunctionNameD0, D1, D2/C, D3/KS0–S3

G0/INT, G1/TOUTG2, G3F0, F1

D0, D1, D2/C, D3/KS0–S3

G0/INT, G1G2, G3F0, F1

High impedance(Note)

Reset releasedPower-onThe contents of timers, registers, flags and RAM except shownin Figure 23 are undefined, so set the initial value to them.

State

Note: Output latch is set to “1.”

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• Program counter (PC)..............................................................0 Address 0 in page 0 is set to program counter.

• Interrupt enable flag (INTE).....................................................0• Power down flag (P).................................................................0• External interrupt request flag (EXF0).....................................0• Timer 1 interrupt request flag (T1F)........................................0• Timer control register V1.........................................................00000000000(Interrupt disabled)

000(Interrupt disabled, prescaler/timer 1 stopped)

• Key-on wakeup control register K0.........................................0000• Pull-up control register PU0.....................................................0• Logic operation selection register LO......................................0• Carry flag (CY).........................................................................0• Register A.................................................................................1• Register B.................................................................................1• Stack pointer (SP)....................................................................1Fig. 23 Internal state at reset

00111

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RAM BACK-UP MODE

The 4250 Group has the RAM back-up mode.

When the POF instruction is executed continuously, systementers the RAM back-up state.

As oscillation stops retaining RAM, the function of reset circuitand states at RAM back-up mode, current dissipation can bereduced without losing the contents of RAM. Table 12 showsthe function and states retained at RAM back-up. Figure 24 showsthe state transition.

(1) Identification of the start condition

Warm start (return from the RAM back-up state) or cold start(return from the normal reset state) can be identified byexamining the state of the power down flag (P) with the SNZPinstruction.(2) Warm start condition

When the external wakeup signal is input after the systementers the RAM back-up state by executing the POF instructioncontinuously, the CPU starts executing the software fromaddress 0 in page 0. In this case, the P flag is “1.”(3) Cold start condition

The CPU starts executing the software from address 0 in page0 when reset pulse is input to RESET pin.In this case, the P flag is “0.”(4) Return signal

An external wakeup signal is used to return from the RAMback-up mode. Table 13 shows the return condition for eachreturn source.Table 13 Return source and return condition

Return sourceG0/INT pin

Table 12 Functions and states retained at RAM back-up

RAM back-upFunctionProgram counter (PC), registers A, B,carry flag (CY), stack pointer (SP) (Note 2)

Contents of RAMPort

Timer control register V1Timer 1 function

Pull-up control register PU0

Key-on wakeup control register K0Logic operation selection register LOExternal interrupt request flag (EXF0)Timer 1 interrupt request flag (T1F)Interrupt enable flag (INTE)

!O!!!OO!!!!

Notes 1: “O” represents that the function can be retained, and

“!” represents that the function is initialized.

Registers and flags other than the above are undefinedat RAM back-up, and set an initial value after returning.2:The stack pointer (SP) points the level of the stackregister and is initialized to “3” at RAM back-up.

Return conditionRemarks

Return by an external rising edgeSelect the return edge (rising edge or falling edge) with the bit 2 of registerinput (“L”→“H”) or falling edgeK0 according to the external state before going into the RAM back-upinput (“H”→“L”).

The EXF0 flag is not set.

state.

Ports G1–G3S0–S3

Return by an external “L” levelSet the port using the key-on wakeup function selected with register K0input.

to “H” level before going into the RAM back-up state.

Note: G0/INT pin and ports G1–G3, S0–S3 share the circuit which is used to detect the edge and to recognize “L” level.

The G0/INT pin cannot be set to “no key-on wakeup.”

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(5) Key-on wakeup control register K0•Key-on wakeup control register K0

The interrupt valid waveform for INT pin/key-on wakeupvalid waveform selection bit, the ports G1–G3 key-onwakeup control bit and the ports S0–S3 key-on wakeupcontrol bit are assigned to the register K0. Set the contentsTable 14 Key-on wakeup control register

Key-on wakeup control register K0K03

Prescaler dividing ratio selection bitInterrupt valid waveform for INT pin/

K02

key-on wakeup valid waveform selectionbit (Note 2)

K01K00

Ports G1–G3 key-on wakeup control bitPorts S0–S3 key-on wakeup control bit

0101010

of this register through register A with the TK0A instruction.The TAK0 instruction can be used to transfer the contentsof register K0 to register A.

at reset : 00002at RAM back-up : state retainedR/W

Instruction clock divided by 4Instruction clock divided by 512Rising waveform (“L” → “H”)Falling waveform (“H” → “L”)

Key-on wakeup not used

Key-on wakeup used (“L” level recognized)Key-on wakeup not used

Key-on wakeup used (“L” level recognized)1

Notes 1: “R” represents read enabled, and “W” represents write enabled.

2: Set a value to the bit 2 of register K0, and execute the SNZ0 instruction to clear the EXF0 flag after executing at least oneinstruction. According to the input state of G0/INT pin, the external interrupt request flag (EXF0) may be set when theinterrupt valid waveform is changed.

AReset(Stabilizing time a )f(XIN) oscillationPOF instruction is executedReturn input(Stabilizing time a )Bf(XIN) stop(RAM back-up mode)Stabilizing time a : Microcomputer starts its operation after 3584 to 3585 machine cycles for the time required to stabilize the f(XIN) oscillation.Fig. 24 State transitionPower down flag PPOF instructionReset inputSRQSoftware startP = “1”?NoCold startYesq Set source POF instruction is executedq Clear source Reset inputFig. 25 Set source and clear source of the P flagWarm startFig. 26 Start condition identified example using the SNZPinstruction

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CLOCK CONTROL

The clock control circuit consists of the following circuits.•System clock generating circuit

•Control circuit to stop the clock oscillation

•Control circuit to return from the RAM back-up state

XINXOUTOscillation circuitInternal clock generating circuit (divided by 4)Instruction clockCounterWait time control circuit (Note)RESETPOF instructionRSQSoftware start signalKey-on wakeup control register K00, K01MultiplexerPorts G1–G3Ports S0–S3K02Rising0G0/INT pinRising detected1FallingNote: The wait time control circuit is used to start the microcomputer operation after 3584 to 3585 machine cycles for the time required to stabilize the f(XIN) oscillation.Fig. 27 Clock control circuit structureClock signal f(XIN) is obtained by connecting XIN pin and XOUTpin directly, and externally connecting a resistor to XIN and acapacitor to XOUT. Connect this external circuit to pins XIN andXOUT at the shortest distance.

When an external clock signal is input, note the input waveform(refer to the list of precaution).

XINXOUTROM ORDERING METHOD

Please submit the information described below when orderingMask ROM.

(1) M34250M2-XXXFP Mask ROM Order Confirmation Form..............................................................................................1(2) Data to be written into mask ROM.........................EPROM(three sets containing the identical data)

(3) Mark Specification Form.....................................................1

The system clock frequency is affected by a capacitor, a resistor and an LSI, So, set the constants within the range of the frequency limits.Fig. 28 Resistor and capacitor external circuitM34250M2-XXXFP29

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LIST OF PRECAUTIONS

󰃀Noise and latch-up preventionConnect a capacitor on the following condition to prevent noiseand latch-up;

•connect a bypass capacitor (approx. 0.01 µF) between pinsVDD and VSS at the shortest distance,

•equalize its wiring in width and length, and•use the thickest wire.

In the One Time PROM version, CNVSS pin is also used asVPP pin. Connect this pin to VSS through the resistor about5 kΩ which is assigned to CNVSS/VPP pin as close aspossible at the shortest distance.󰃁PrescalerStop the prescaler operation to change its frequency dividingratio.󰃂Timer count sourceStop timer 1 counting to change its count source.

󰃃Program counterMake sure that the PCH does not specify after the last page ofthe built-in ROM.󰃄G0/INT pin

When the interrupt valid waveform of the G0/INT pin is changedwith the bit 2 of register K0 in software, be careful about thefollowing notes.

•After clear the bit 0 of register V1 to “0” (Figure 29󰃀),change the interrupt valid waveform of G0/INT pin with thebit 2 of register K0 .

•Set a value to bit 2 of register K0 and execute the SNZ0instruction to clear the external interrupt request flag (EXF0)after executing at least one instruction (refer to Figure 29󰃁).Depending on the input state of the G0/INT pin, the EXF0flag may be set when the interrupt valid waveform ischanged.

󰃅Notes on unused pins•When pins G0/INT, G1/TOUT, G2 and G3 are connected toVSS pin, turn off their pull-up transistors (register PU0=“!02”)and also invalidate the key-on wakeup functions of pinsG1/TOUT, G2 and G3 (register K0=“!!0!2”) by software.When the POF instruction is executed while these pins areconnected to VSS and the key-on wakeup functions are leftvalid, the system returns from RAM back-up state byrecognizing the return condition immediately after going intothe RAM back-up state. When these pins are open, turn ontheir pull-up transistors (register PU0=“!12”) by software.•When ports S0–S3 are connected to VSS pin, invalidate thekey-on wakeup functions (register K0=“!!!02”) bysoftware. When the POF instruction is executed while thesepins are connected to VSS and the key-on wakeup functionsare left valid, the system returns from RAM back-up stateby recognizing the return condition immediately after goinginto the RAM back-up state.•When ports D2/C and D3/K are connected to VSS pin, turnoff their pull-up transistors (register PU0=“0!2”) by software.When these pins are open, turn on their pull-up transistors(register PU0=“1!2”) by software.(Note when connecting to VSS and VDD)

•Connect the unused pins to VSS or VDD at the shortest distance(within 20 mm) and use the thick wire against noise.󰃆Multifunction

•G0/INT pin can be also used as an I/O port G0 even when itis used as INT pin.

•G1/TOUT pin can be also used as input port G1 even when itis used as TOUT pin.

•D2/C pin can be also used as I/O port D2 even when it isused as port C.

•D3/K pin can be also used as I/O port D3 even when it isused as port K.

...LA 4TV1ALA 4TK0ANOPSNZ0NOP...

; (!!!02)

; The SNZ0 instruction is valid.............󰃀; Change of the interrupt valid waveform..............................................................󰃁

; The SNZ0 instruction is executed

! : this bit is not related to the setting of G0/INT pin.

Fig. 29 External interrupt program example30

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󰃇Key-on wakeupWhen system returns from RAM back-up state by using theG0/INT pin, select the return edge (rising edge or falling edge)with the bit 2 of register K0 according to the external statebefore going into the RAM back-up state.

When system returns from RAM back-up state by using theports G1–G3 and S0–S3, set the port using the key-on wakeupfunction selected with register K0 to “H” level before going intothe RAM back-up state.

G0/INT pin and ports G1–G3, S0–S3 share the circuit which isused to detect the edge and to recognize “L” level.The G0/INT pin cannot be set to “no key-on wakeup.”󰃈External clock input waveform

When the external clock is used, open XOUT pin, and input theclock waveform into XIN pin shown below. (Refer to Figure 30)•Duty ratio = 50 %.

•“H” level input voltage=VDD (V), “L” level input voltage=VSS (V).

VDD(V)VSS(V)t/2 (S)t/2 (S)t (S)Fig. 30 External clock input waveform󰃉CR oscillation constant

Use the external 30 pF capacitor and enable to change thefrequency by the external resistor.

Test the system sufficiently because the oscillation constantdepends on the ROM type (mask ROM or PROM).

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SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER

SYMBOL

The symbols shown below are used in the following list of instruction function and the machine instructions.

SymbolABDREV1K0PU0LOXYDPPCPCHPCLSKSPCYR1T1T1FINTEEXF0P

Timer control register V1 (4 bits)

Key-on wakeup control register K0 (4 bits)Pull-up control register PU0 (2 bits)

Logic operation selection register LO (2 bits)Register X (2 bits)Register Y (4 bits)Data pointer (6 bits)

(It consists of registers X and Y)Program counter (11 bits)

High-order 4 bits of program counterLow-order 7 bits of program counterStack register (11 bits ! 4)Stack pointer (2 bits)Carry flag

Timer 1 reload registerTimer 1

Timer 1 interrupt request flagInterrupt enable flag

External interrupt request flagPower down flag

←↔?( )—M(DP)ap, aC +x

Note :The 4250 Group just invalidates the next instruction when a skip is performed. The contents of program counter is not

increased by 2. Accordingly, the number of cycles does not change even if skip is not performed. However, the cycle countbecomes “1” if the TABP p, RT, or RTS instruction is skipped.

xypnj

A3A2A1A0

Hexadecimal variableHexadecimal variableHexadecimal variable

Hexadecimal constant which represents theimmediate value

Binary notation of hexadecimal variable A(same for others)

Direction of data movement

Data exchange between a register and memoryDecision of state shown before “?”Contents of registers and memoriesNegate, Flag unchanged after executinginstruction

RAM address pointed by the data pointerLabel indicating address a6 a5 a4 a3 a2 a1 a0Label indicating address a6 a5 a4 a3 a2 a1 a0in page p3 p2 p1 p0

Hex. C + Hex. number x (also same for others)

Contents

DFGSKCSymbol

Port D (4 bits)Port F (2 bits)Port G (4 bits)Port S (4 bits)Port K (1 bit)Port C (1 bit)

Contents

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MITSUBISHI MICROCOMPUTERS

4250 Group

SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER

LIST OF INSTRUCTION FUNCTION

GroupingMnemonic

Function

(A) ← (B)(B) ← (A)

GroupingMnemonicFunction

(A) ← nn = 0 to 15(SP) ← (SP) + 1(SK(SP)) ← (PC)(PCH) ← p

(PCL) ← (DR2–DR0,A3–A0)

(B) ← (ROM(PC))7 to 4(A) ← (ROM(PC))3 to 0(PC) ← (SK(SP))(SP) ← (SP) – 1

GroupingMnemonicFunction

(A) = (M(DP)) ?(A) = n ?n = 0 to 15

ComparisonTABTBARegister to register transferTAYTYATEAB

LA nSEAMoperationSEA n

TABP p

(A) ← (Y)(Y) ← (A)(E7–E4) ← (B)(E3–E0) ← (A)

TABE

(B) ← (E7–E4)(A) ← (E3–E0)

TDALXY x, yRAM addresses(DR2–DR0) ← (A2–A0)

Arithmetic operationAMC

(X) ← x, x = 0 to 3(Y) ← y, y = 0 to 15

INYDEYTAM j

(Y) ← (Y) + 1(Y) ← (Y) – 1

(A) ← (M(DP))(X) ← (X) EXOR(j)j = 0 to 3

XAM j

(A) ←→ (M(DP))(X) ← (X) EXOR(j)j = 0 to 3

RAM to register transferRAR

XAMD j

(A) ←→ (M(DP))(X) ← (X) EXOR(j)j = 0 to 3

(Y) ← (Y) – 1

XAMI j

(A) ←→ (M(DP))(X) ← (X) EXOR(j)

Bit operationj = 0 to 3(Y) ← (Y) + 1

SB jLGOPRCSZCCMA

B aBranch operationBL p, a

(PCL) ← a6–a0(PCH) ← p(PCL) ← a6–a0

BA aBLA p, a

(PCL) ← (a6–a4, A3–A0)(PCH) ← p

(PCL) ← (a6–a4, A3–A0)(SP) ← (SP) + 1(SK(SP)) ← (PC)(PCH) ← 2(PCL) ← a6–a0

(A) ← (A) + (M(DP))(A) ← (A) + (M(DP)) + (CY)(CY) ← Carry

Subroutine operationBM a

A n(A) ← (A) + nn = 0 to 15(CY) ← 1(CY) ← 0(CY) = 0 ?(A) ← (A)

→ CY → A3A2A1A0Logic operationinstruction

XOR, OR, AND(Mj(DP)) ← 1j = 0 to 3(Mj(DP)) ← 0j = 0 to 3(Mj(DP)) = 0 ?j = 0 to 3

BML p, a(SP) ← (SP) + 1

(SK(SP)) ← (PC)(PCH) ← p

(PCL) ← a6–a0

BMLA p,(SP) ← (SP) + 1

(SK(SP)) ← (PC)a

(PCH) ← p

(PCL) ← (a6–a4, A3–A0)

RTI

(PC) ← (SK(SP))(SP) ← (SP) – 1(PC) ← (SK(SP))(SP) ← (SP) – 1(PC) ← (SK(SP))(SP) ← (SP) – 1

RTReturn operationRTS

RB j

SZB j

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MITSUBISHI MICROCOMPUTERS

4250 Group

SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER

LIST OF INSTRUCTION FUNCTION (CONTINUED)

GroupingMnemonic

Function

INTE← 0INTE ← 1(EXF0) = 1 ?

After skipping the nextinstruction(EXF0) ← 0

GroupingMnemonicFunction

(D) ← 1(D(Y)) ← 0(Y) = 0 to 3

GroupingMnemonicFunction(PC) ← (PC) + 1RAM back-up(P) = 1 ?(LO) ← (A1, A0)(V1) ← (A)(A) ← (V1)(K0) ← (A)(A) ← (K0)(PU0) ← (A)

DIInterrupt operationEISNZ0

CLDRD

NOPPOFSNZP

SD(D(Y)) ← 1

Other operation(Y) = 0 to 3

TLOATV1ATAV1TK0A

SZD

TAB1Timer operation(B) ← (T17–T14)(A) ← (T13–T10)(R17–R14) ← (B)(T17–T14) ← (B)(R13–R10) ← (A)(T13–T10) ← (A)

SNZ1

(T1F) = 1 ?

After skipping the nextinstruction(T1F) ← 0

OGAIAGOSAIASOKAIAKInput/Output operationSCPRCPSNZCPOFAIAF

(D(Y)) = 0 ?(Y) = 0 to 3(C) ← 1(C) ← 0

T1AB

TAK0

TPU0A

(F) ← (A1, A0)(A1, A0) ← (F)(A3, A2) ← (0)(G) ← (A)(A) ← (G)(S) ← (A)(A) ← (S)(K) ← (A0)(A0) ← (K),

(A3, A2, A1) ← (0)

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MITSUBISHI MICROCOMPUTERS

4250 Group

SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER

INSTRUCTION CODE TABLE

D8–D400000000010001000011001000010100110001110100001001010100101101100011010111001111D3–D0Hex.notation1000011000101111111110 to 1718 to 1F––00NOPBA01BLACLD02SZB 0SZB 1SZB 203BLBLBLBLBLBLBLBL0405BMLA06XAM 0XAM 1XAM 2XAM 307BMLBMLBMLBMLBMLBMLBMLBMLBMLBMLBML08090AA0A1A2A3A4A5A6A7A8A9 A10 A11 A12 A13 A14 A150BLA 0LA 1LA 2LA 3LA 4LA 5LA 6LA 7LA 8LA 9 LA 10 LA 11 LA 12 LA 13 LA 14 LA 150CLXY 0,0LXY 0,1LXY 0,2LXY 0,3LXY 0,4LXY 0,5LXY 0,6LXY 0,7LXY 0,8LXY 0,90DLXY 1,0LXY 1,1LXY 1,2LXY 1,3LXY 1,4LXY 1,5LXY 1,6LXY 1,7LXY 1,8LXY 1,90ELXY 2,0LXY 2,1LXY 2,2LXY 2,3LXY 2,4LXY 2,5LXY 2,6LXY 2,7LXY 2,8LXY 2,90FLXY 3,0LXY 3,1LXY 3,2LXY 3,3LXY 3,4LXY 3,5LXY 3,6LXY 3,7LXY 3,8LXY 3,900000001001000110100010101100111100010011010101111001101111011110123456789OGATABP 0OKASCPRCPOFAT1ABTV1ATK0ATAV1TAK0TABP 1TABP 2TABP 3TABP 4TABP 5TABP 6TABP 7TABP 8TABP 9BMBMBMBMBMBMBMBBBBBBBBBBBLGOPSNZPDIEIRCSCINYRDSDSZB 3SZDSEAnRTRTSRTIIASIAFIAKTAM 0TAM 1TAM 2TAM 3SEAMDEYIAGTDABMBMBMBMBMBMBMBMBMBLBLBLBLBLBLBLRB 0RB 1RB 2RB 3XAMITLOA 0XAMI 1XAMI 2XAMI 3SB 0SB 1SB 2SB 3ABCDEFAMAMCTYAPOFTBATEABTABEOSACMARARTABTAYSZCTABPTAB1 10TABP 11 LXY LXY LXY LXY 0,10 1,10 2,10 3,10 LXY LXY LXY LXY 0,11 1,11 2,11 3,11 LXY LXY LXY LXY 0,12 1,12 2,12 3,12 LXY LXY LXY LXY 0,13 1,13 2,13 3,13 LXY LXY LXY LXY 0,14 1,14 2,14 3,14 LXY LXY LXY LXY 0,15 1,15 2,15 3,15BMLTPU0ABBBBB TABPXAMDBMLSNZ1 12 0XAMDTABPBMLSNZCP 1 13XAMDBML 2TABP 14BLXAMDTABPBMLSNZ0 3 15The above table shows the relationship between machine language codes and machine language instructions. D3–D0

show the low-order 4 bits of the machine language code, and D8–D4 show the high-order 5 bits of the machine language code. The hexadecimal representation of the code is also provided. There are one-word instructions and two-word instructions, but only the first word of each instruction is shown.

The codes for the second word of a two-word instruction are described below.

BLBMLBABLABMLASEASZDThe second word1 1 a a a a a a a1 0 a a a a a a a 1 1 a a a a a a a 1 1 a a a p p p p1 0 a a a p p p p0 1 0 1 1 n n n n 0 0 0 1 0 1 0 1 1Do not use the code marked “–.”

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MITSUBISHI MICROCOMPUTERS

4250 Group

SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER

MACHINE INSTRUCTIONS

Number ofwordsParameterMnemonicType ofinstructionsNumber ofcyclesInstruction codeD8D7D6D5D4D3D2D1D0TABTBATAYTYATEABTABETDALXY x, y000000000000000100000001000001110101001111111111100011101100010001HexadecimalnotationFunction01000100010202EEFCAA91111111111111111(A) ← (B)(B) ← (A)(A) ← (Y)(Y) ← (A)(E7–E4) ← (B) (E3–E0) ← (A)(B) ← (E7–E4) (A) ← (E3–E0)(DR2–DR0) ← (A2–A0)(X) ← x, x = 0 to 3(Y) ← y, y = 0 to 15Register to register transferx1x0y3y2y1y00Cy+xRAM addressesINY00001001101311(Y) ← (Y) + 1DEY00001011101711(Y) ← (Y) – 136

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MITSUBISHI MICROCOMPUTERS

4250 Group

SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER

Skip conditionCarry flag CYDetailed description–––––––Continuousdescription––––––––Transfers the contents of register B to register A.Transfers the contents of register A to register B.Transfers the contents of register Y to register A.Transfers the contents of register A to register Y.Transfers the contents of registers A and B to register E.Transfers the contents of register E to registers A and B.Transfers the contents of register A to register D.Loads the value x in the immediate field to register X, and the value y in the immediate field to registerY.When the LXY instructions are continuously coded and executed, only the first LXY instruction is executedand other LXY instructions coded continuously are skipped.(Y) = 0–Adds 1 to the contents of register Y. As a result of addition, when the contents of register Y is 0, thenext instruction is skipped.(Y) = 15–Subtracts 1 from the contents of register Y. As a result of subtraction, when the contents of register Yis 15, the next instruction is skipped.37

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MITSUBISHI MICROCOMPUTERS

4250 Group

SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER

MACHINE INSTRUCTIONS (CONTINUED)

Number ofwordsParameterMnemonicType ofinstructionsNumber ofcyclesInstruction codeD8D7D6D5D4D3D2D1D0TAM j0011001j1j0HexadecimalnotationFunction064+j11(A) ← (M(DP))(X) ← (X) EXOR(j)j = 0 to 3RAM to register transferXAM j0011000j1j006j11(A) ←→ (M(DP))(X) ← (X) EXOR(j)j = 0 to 3XAMD j0011011j1j006C+j11(A) ←→ (M(DP))(X) ← (X) EXOR(j)j = 0 to 3(Y) ← (Y) – 1XAMI j0011010j1j0068+j11(A) ←→ (M(DP))(X) ← (X) EXOR(j)j = 0 to 3(Y) ← (Y) + 138

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MITSUBISHI MICROCOMPUTERS

4250 Group

SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER

Skip conditionCarry flag CYDetailed description––After transferring the contents of M(DP) to register A, an exclusive OR operation is performed betweenregister X and the value j in the immediate field, and stores the result in register X.––After exchanging the contents of M(DP) with the contents of register A, an exclusive OR operation isperformed between register X and the value j in the immediate field, and stores the result in register X.(Y) = 15–After exchanging the contents of M(DP) with the contents of register A, an exclusive OR operation isperformed between register X and the value j in the immediate field, and stores the result in register X.Subtracts 1 from the contents of register Y. As a result of subtraction, when the contents of register Yis 15, the next instruction is skipped.(Y) = 0–After exchanging the contents of M(DP) with the contents of register A, an exclusive OR operation isperformed between register X and the value j in the immediate field, and stores the result in register X.Adds 1 to the contents of register Y. As a result of addition, when the contents of register Y is 0, thenext instruction is skipped.39

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MITSUBISHI MICROCOMPUTERS

4250 Group

SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER

MACHINE INSTRUCTIONS (CONTINUED)

Number ofwordsParameterMnemonicType ofinstructionsNumber ofcyclesInstruction codeD8D7D6D5D4D3D2D1D0LA n01011n3n2n1n0HexadecimalnotationFunction0Bn11(A) ← nn = 0 to 15TABP p01001p3p2p1p009p13(SK(SP)) ← (PC)(SP) ← (SP) + 1(PCH) ← p(PCL) ← (DR2–DR0, A3–A0)(B) ← (ROM(PC))7 to 4(A) ← (ROM(PC))3 to 0(SP) ← (SP) – 1(PC) ← (SK(SP))(Note)AMArithmetic operation00000101000A11(A) ← (A) + (M(DP))AMC00000101100B11(A) ← (A) + (M(DP))+ (CY)(CY) ← CarryA n01010n3n2n1n00An11(A) ← (A) + nn = 0 to 15SCRCSZCCMARARLGOP00000000000100000000100000011000111011111011100010101100000201010476FCD1111111111111(CY) ← 1(CY) ← 0(CY) = 0 ?(A) ← (A)→ CY → A3A2A1A0Logic operation instruction XOR, OR, ANDNote :p is 0 to 15 for M34250E2, and p is 0 to 15 for M34250M2.40

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MITSUBISHI MICROCOMPUTERS

4250 Group

SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER

Skip conditionCarry flag CYDetailed descriptionContinuousdescription–Loads the value n in the immediate field to register A.When the LA instructions are continuously coded and executed, only the first LA instruction is executedand other LA instructions coded continuously are skipped.––Transfers bits 7 to 4 to register B and bits 3 to 0 to register A. These bits 7 to 0 are the ROM pattern inaddress (DR2 DR1 DR0 A3 A2 A1 A0) specified by registers A and D in page p.When this instruction is executed, 1 stage of stack register is used.––Adds the contents of M(DP) to register A. Stores the result in register A. The contents of carry flag CYremains unchanged.–0/1Adds the contents of M(DP) and carry flag CY to register A. Stores the result in register A and carry flagCY.Overflow = 0–Adds the value n in the immediate field to register A.The contents of carry flag CY remains unchanged.Skips the next instruction when there is no overflow as the result of operation.––(CY) = 0–––10––Sets (1) to carry flag CY.Clears (0) to carry flag CY.Skips the next instruction when the contents of carry flag CY is “0.”Stores the one‘s complement for register A‘s contents in register A.0/1Rotates 1 bit of the contents of register A including the contents of carry flag CY to the right.–Execute the logic operation selected by logic operation selection register LO between the contents ofregister A and port S, and stores the result in register A.41

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MITSUBISHI MICROCOMPUTERS

4250 Group

SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER

MACHINE INSTRUCTIONS (CONTINUED)

Number ofwordsParameterMnemonicType ofinstructionsNumber ofcyclesInstruction codeD8D7D6D5D4D3D2D1D0SB j0010111j1j0HexadecimalnotationFunction05C+j11(Mj(DP)) ← 1j = 0 to 3Bit operationRB j0010011j1j004C+j11(Mj(DP)) ← 0j = 0 to 3SZB j0001000j1j002j11(Mj(DP)) = 0 ?j = 0 to 3SEAMComparisonoperationSEA n0000011000111001001110010202651212(A) = (M(DP)) ?(A) = n ?n = 0 to 15n3n2n1n00Bn18+aa11(PCL) ← a6–a0B a1a6a5a4a3a2a1a0BL p, a00011p3p2p1p003p22(PCH) ← p(PCL) ← a6–a0(Note)Branch operation11a6a5a4a3a2a1a018+aaBA a0101000000100122(PCL) ← (a6–a4, A3–A0)a6a5a4a3a2a1a018a+a0118+a0p22(PCH) ← p(PCL) ← (a6–a4, A3–A0)(Note)BLA p, a01010010000a6a5a4p3p2p1p0Note :p is 0 to 15 for M34250E2, and p is 0 to 15 for M34250M2.42

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MITSUBISHI MICROCOMPUTERS

4250 Group

SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER

Skip conditionCarry flag CYDetailed description––Sets (1) the contents of bit j (bit specified by the value j in the immediate field) of M(DP).––Clears (0) the contents of bit j (bit specified by the value j in the immediate field) of M(DP).(Mj(DP)) = 0j = 0 to 3(A) = (M(DP))(A) = nn = 0 to 15–Skips the next instruction when the contents of bit j (bit specified by the value j in the immediate field)of M(DP) is “0.”––Skips the next instruction when the contents of register A is equal to the contents of M(DP).Skips the next instruction when the contents of register A is equal to the value n in the immediate field.––Branch within a page : Branches to address a in the identical page.––Branch out of a page : Branches to address a in page p.––Branch within a page : Branches to address (a6 a5 a4 A3 A2 A1 A0) determined by replacing the low-order 4 bits of the address a with register A in the identical page.––Branch out of a page : Branches to address (a6 a5 a4 A3 A2 A1 A0) determined by replacing the low-order 4 bits of the address a with register A in page p.43

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MITSUBISHI MICROCOMPUTERS

4250 Group

SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER

MACHINE INSTRUCTIONS (CONTINUED)

Number ofwordsParameterMnemonicType ofinstructionsNumber ofcyclesInstruction codeD8D7D6D5D4D3D2D1D0BM a10a6a5a4a3a2a1a0HexadecimalnotationFunction1aa11(SK(SP)) ← (PC)(SP) ← (SP) + 1(PCH) ← 2(PCL) ← a6–a0Subroutine operationBML p, a00111p3p2p1p007p22(SK(SP)) ← (PC)(SP) ← (SP) + 1(PCH) ← p(PCL) ← a6–a0(Note)10a6a5a4a3a2a1a01aaBMLA p, a01001010000051a0p22(SK(SP)) ← (PC)(SP) ← (SP) + 1(PCH) ← p(PCL) ← (a6–a4, A3–A0)(Note)a6a5a4p3p2p1p0RTIReturn operation00100011004611(PC) ← (SK(SP))(SP) ← (SP) – 1RT00100010004412(PC) ← (SK(SP))(SP) ← (SP) – 1RTS00100010104512(PC) ← (SK(SP))(SP) ← (SP) – 1DIInterrupt operationEISNZ0000001000000000001111001011000045111111(INTE) ← 0(INTE) ← 1(EXF0) = 1 ?After skipping the next instruction(EXF0) ← 008FNote :p is 0 to 15 for M34250E2, and p is 0 to 15 for M34250M2.44

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MITSUBISHI MICROCOMPUTERS

4250 Group

SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER

Skip conditionCarry flag CYDetailed description––Call the subroutine in page 2 : Calls the subroutine at address a in page 2.––Call the subroutine : Calls the subroutine at address a in page p.––Call the subroutine : Calls the subroutine at address (a6 a5 a4 A3 A2 A1 A0) determined by replacing thelow-order 4 bits of address a with register A in page p.––Returns from interrupt service routine to main routine.Returns each value of data pointer (X, Y), carry flag, skip status, NOP mode status by the continuousdescription of the LA/LXY instruction to the states just before interrupt.––Returns from subroutine to the routine called the subroutine.Skip at uncondition–Returns from subroutine to the routine called the subroutine, and skips the next instruction at uncondition.––(EXF0) = 1–––Clears (0) to the interrupt enable flag INTE, and disables the interrupt.Sets (1) to the interrupt enable flag INTE, and enables the interrupt.Skips the next instruction when the contents of EXF0 flag is “1.”After skipping, clears the EXF0 flag.45

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MITSUBISHI MICROCOMPUTERS

4250 Group

SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER

MACHINE INSTRUCTIONS (CONTINUED)

Number ofwordsParameterMnemonicType ofinstructionsNumber ofcyclesInstruction codeD8D7D6D5D4D3D2D1D0TAB1010001010HexadecimalnotationFunction08A11(B) ← (T17–T14)(A) ← (T13–T10)Timer operationT1AB01000010108511(R17–R14) ← (B)(T17–T14) ← (B)(R13–R10) ← (A)(T13–T10) ← (A)SNZ101000110008C11(T1F) = 1 ?After skipping the next instruction(T1F) ← 0CLDRD0000000011000100100110141111(D) ← 1(D(Y)) ← 0(Y) = 0 to 3(D(Y)) ← 1(Y) = 0 to 3(D(Y)) = 0 ?(Y) = 0 to 3Input/Output operationSD00001010101511SZD00000011000110010102402B2246

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MITSUBISHI MICROCOMPUTERS

4250 Group

SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER

Skip conditionCarry flag CYDetailed description––Transfers the contents of timer 1 to registers A and B.––Transfers the contents of registers A and B to timer 1 and timer 1 reload register.(T1F) = 1–Skips the next instruction when the contents of T1F flag is “1.”After skipping, clears (0) to T1F flag.––––Sets (1) to port D (high-impedance state).Clears (0) to a bit of port D specified by register Y.––Sets (1) to a bit of port D specified by register Y (high-impedance state).(D(Y)) = 0(Y) = 0 to 3–Skips the next instruction when a bit of port D specified by register Y is “0.”47

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MITSUBISHI MICROCOMPUTERS

4250 Group

SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER

MACHINE INSTRUCTIONS (CONTINUED)

Number ofwordsParameterMnemonic

Type ofinstructions

Number ofcyclesInstruction code

D8D7D6D5D4D3D2D1D0

OFAIAFOGAIAG

0000000000000

1010001011100

0100010100000

0001000000000

0100110100000

0001100000101

1100010100101

0100100111000

0000111101101

Hexadecimalnotation

Function

08405608002801B05508105708208308D0000

1111111111111

(F) ← (A1, A0)

(A1, A0) ← (F), (A3, A2) ← 0(G) ← (A)(A) ← (G)(S) ← (A)(A) ← (S)(K) ← (A0)

(A0) ← (K), (A3–A1) ← 0(C) ← 1(C) ← 0(C) = 1 ?(PC) ← (PC) + 1RAM back-up

Input/Output operationOSAIASOKAIAKSCPRCPSNZCPNOPPOF

SNZP

Other operation00000001100311(P) = 1 ?

TLOATV1ATAV1TK0ATAK0TPU0A

000000

011111

100000

000000

100000

101011

010100

010101

000111

050808080808

86879B

111111

(LO) ← (A1, A0)(V1) ← (A)(A) ← (V1)(K0) ← (A)(A) ← (K0)(PU0) ← (A)

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SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER

Skip condition

Carry flag CYDetailed description

––––––––––(C) = 1––

–––––––––––––

Outputs the contents of register A to port F.Transfers the contents of port F to register A.Outputs the contents of register A to port G.Transfers the contents of port G to register A.Outputs the contents of register A to port S.Transfers the contents of port S to register A.Outputs the contents of register A to port K.Transfers the contents of port K to register A.Sets (1) to port C.Clears (0) to port C.

Skips the next instruction when the contents of port C is “1.”No operation

Puts the system in RAM back-up state.

(P) = 1–

Skips the next instruction when P flag is “1.”After skipping, P flag remains unchanged.

Transfers the contents of register A to the logic operation selection register LO.Transfers the contents of register A to register V1.Transfers the contents of register V1 to register A.Transfers the contents of register A to register K0.Transfers the contents of register K0 to register A.Transfers the contents of register A to register PU0.

––––––

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4250 Group

SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER

CONTROL REGISTERS

Timer control register V1

V13V12V11V10

G1/TOUT pin function selection bitPrescaler/timer 1 operation start bitTimer 1 interrupt enable bitExternal interrupt enable bitKey-on wakeup control register K0K03

Prescaler dividing ratio selection bitInterrupt valid waveform for INT pin/

K02

key-on wakeup valid waveform selectionbit (Note 2)

Ports G1–G3 key-on wakeup control bitPorts S0–S3 key-on wakeup control bitPull-up control register PU0

PU01PU00

Ports C and K

pull-up transistor control bitPorts G0–G3

pull-up transistor control bitLogic operation selection register LOLO1

Logic operation function selection bits

LO0

01010101010101010101

at reset : 00002

Port G1 (I/O)

TOUT pin (output) / port G1(input)

Prescaler stop (initial state) / timer 1 stop (state retained)Prescaler/timer 1 operation

at RAM back-up : state retained

R/W

at RAM back-up : 00002

R/W

Instruction clock divided by 4Instruction clock divided by 512Rising waveform (“L” → “H”)Falling waveform (“H” → “L”)Key-on wakeup not used

Key-on wakeup used (“L” level recognized)Key-on wakeup not used

Key-on wakeup used (“L” level recognized)at reset : 002

Pull-up transistor ONPull-up transistor OFFPull-up transistor ONat reset : 002

at RAM back-up : 002Functions

at RAM back-up : state retained

K01K00

Pull-up transistor OFF

LO1LO0

0XOR operation0

1OR operation0

0AND operation1

1Not available1

Notes 1: “R” represents read enabled, and “W” represents write enabled.

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MITSUBISHI MICROCOMPUTERS

4250 Group

SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER

ABSOLUTE MAXIMUM RATINGS

SymbolParameterVDDSupply voltageVIInput voltage XIN, G0–G3, D2/C, D3/KVIInput voltage F0, F1, S0–S3, D0, D1, RESETVOOutput voltage XOUTVOVOPdToprTstg

Output voltage F0, F1, S0–S3, D0, D1Output voltage G0–G3, D2/C, D3/KPower dissipation

Operating temperature rangeStorage temperature range

Conditions

Ratings

–0.3 to 7.0–0.3 to VDD+0.3–0.3 to 8.0

–0.3 to VDD+0.3

Output transistorsin cut-off stateTa = 25 °C

–0.3 to 8.0–0.3 to VDD+0.3300–20 to 85–40 to 125

UnitVVVVVVmW°C

°C

RECOMMENDED OPERATING CONDITIONS

(Ta = –20 °C to 85 °C, VDD = 2.2 V to 5.5 V, unless otherwise noted)SymbolVDDVRAMVSSVIHVIHVIHVIHVIHVIHVILVILVILVIL

Supply voltage

RAM back-up voltage (at RAM back-up mode)Supply voltage

“H” level input voltage F0, F1, D0, D1“H” level input voltage G0–G3, D2, D3“H” level input voltage INT“H” level input voltage C, K“H” level input voltage S0–S3“H” level input voltage RESET“L” level input voltage C, K“L” level input voltage S0–S3

“L” level input voltage F0, F1, G0–G3, D0–D3“L” level input voltage INT“L” level input voltage RESET

VDD = 4.5 V to 5.5 VVDD = 2.2 V to 5.5 VVDD = 4.5 V to 5.5 VVDD = 2.2 V to 5.5 V

Parameter

Conditions

0.4 MHz ≤ f(XIN) ≤ 4.4 MHz0.4 MHz ≤ f(XIN) ≤ 1.1 MHz

Limits

Min.4.52.22.0

0.7VDD0.7VDD0.85VDD0.5VDD0.7VDD0.4VDD0.6VDD0.85VDD

0000

7VDDVDDVDDVDD7770.16VDD0.2VDD0.3VDD0.15VDD

Typ.5.0

Max.5.55.55.5

UnitVVVVVVVVVVVVVVVVV

VIL

IOL(peak)“L” level peak output current0.1VDD24mA101254.41.1±17

%mAmAmAMHz

F0, F1, S0–S3, D0, D1, D2/C, D3/K

IOL(peak)“L” level peak output current G0, G1/TOUT, G2, G3IOL(avg)“L” level average output current

F0, F1, S0–S3, D0, D1, D2/C, D3/K

IOL(avg)“L” level average output current G0, G1/TOUT, G2, G3f(XIN)System clock frequency (Note 2)∆f(XIN)

(Note 1)(Note 1)

VDD = 4.5 V to 5.5 V

VDD = 2.2 V to 5.5 V

0.40.4

4.01.0

Frequency error (errors of external capacitor and resistorVDD = 5 V ±10 %

Ta = 25 °C [reference]not included)

Note: Use the 30 pF capacitor externally and enable the(–20 °C to 85 °C)

change of frequency by external resistor.

VDD = 3 V ±10 %

±17

Ta = 25 °C [reference](–20 °C to 85 °C)

Notes 1: Keep the total currents of IOL(avg) for ports S0–S3, D0, D1, D2/C, D3/K to 50 mA or less.

Keep the total currents of IOL(avg) for ports F0, F1, G0, G2, G3 and G1/TOUT pin to 30 mA or less.

2: The system clock frequency is affected by the external capacitor, resistor and LSI. Accordingly, set the constants so as notto exceed the frequency limits.

Be careful about the input waveform when using the external clock. Refer to the notes on use.

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MITSUBISHI MICROCOMPUTERS

4250 Group

SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER

ELECTRICAL CHARACTERISTICS

(Ta = –20 °C to 85 °C, VDD = 2.2 V to 5.5 V, unless otherwise noted)SymbolVOLVOLIIHIIHIIL

Parameter

“L” level output voltage

F0, F1, S0–S3, D0, D1, D2/C, D3/K“L” level output voltageG0, G1/TOUT, G2, G3

“H” level input current

F0, F1, S0–S3, D0, D1, RESET“H” level input current

G0/INT, G1, G2, G3, D2/C, D3/K“L” level input current

F0, F1, S0–S3, D0, D1, D2/C, D3/K,

IOZHIOZHIDD

G0/INT, G1, G2, G3, RESETOutput current at off-stateF0, F1, S0–S3, D0, D1

Output current at off-state

G0, G1/TOUT, G2, G3, D2/C, D3/KSupply currentat active mode

at RAM back-up mode

VO = VDDVDD = 5 VVDD = 3 VTa = 25 °CVDD = 5 VVDD = 3 V

RPUVT+ – VT–

Pull-up transistor

G0/INT, G1, G2, G3, D2/C, D3/KHysteresis INT

VDD = 5 VVDD = 5 V

0.1

1.8

VDD = 5 V, VI = 0 V

110.3

f(XIN) = 4.0 MHzf(XIN) = 1.0 MHz

1.50.30.1

151110625

VO = 7 V

Test conditions

VDD = 5 VVDD = 3 VVDD = 5 VVDD = 3 VVI = 7 VVI = VDD

VI = 0 V (Note)

IOL = 12 mAIOL = 6 mAIOL = 5 mAIOL = 2 mA

Limits

Min.

Typ.

Max.20.920.911–1

UnitVVVV

µAµAµA

µAµA

mAmA

µAµAµAkΩ

VVVV

VT+ – VT–Hysteresis S0–S3VT+ – VT–Hysteresis RESETVDD = 3 V0.7

Note: In this case, the pull-up transistors for G0/INT pin and ports G1, G2, G3, D2/C and D3/K are not selected.

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MITSUBISHI MICROCOMPUTERS

4250 Group

SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER

BASIC TIMING DIAGRAM

Machine cycleMiT4T1T2Mi+1T3T4ParameterClockPorts D, C, K outputPorts D, C, K inputPorts F, G, S outputPin nameStateXIND0,D1D2/C,D3/KD0,D1D2/C,D3/KF0,F1G0/INT,G1/TOUTG2, G3S0–S3F0,F1G0/INT,G1/TOUTG2, G3S0–S3G0/INTPorts F, G, S inputInterrupt input53

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MITSUBISHI MICROCOMPUTERS

4250 Group

SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER

BUILT-IN PROM VERSION

In addition to the mask ROM versions, the 4250 Group has theOne Time PROM versions whose PROMs can only be written toand not be erased.

The built-in PROM version has functions similar to those of themask ROM versions, but it has PROM mode that enables writingto built-in PROM.

Table 15 Product of built-in PROM version

PROM size

Product

(! 9 bits)M34250E2-XXXFP *M34250E2FP*

*: Under development

2048 words

Table 15 shows the product of built-in PROM version. Figure 31and 32 show the pin configurations of built-in PROM versions.The One Time PROM version has pin-compatibility with the maskROM version.

RAM size(! 4 bits)64 words

PackageROM type

One Time PROM [shipped after writing]

20P2N-A

(shipped after writing and test in factory)One Time PROM [shipped in blank]

PIN CONFIGURATION (TOP VIEW)VDDVSSXINXOUTCNVSSRESETF0F1G0/INTG1/TOUT122019D0D1D2/CD3/KS0S1S2S3G3G2M34250E2-XXXFP3456789101817161514131211Outline 20P2N-AFig. 31 Pin configuration of built-in PROM version54

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MITSUBISHI MICROCOMPUTERS

4250 Group

SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER

PIN CONFIGURATION (TOP VIEW)VDDVSSVVDDVSS(0V)X INX OUT122019D0D1D2/CD3/KS0S1S2S3G3G2M34250E2-XXXFP34567891817161514131211VPPCNVSSRESETSCLKSDAPGMVDDF0F1G0/INTG1/TOUT10Outline 20P2N-AV : A resistor is connected to XIN pin. A capacitor is connected to XOUT pin.Note: The state of each disconnected pin is the same as that at reset.Fig. 32 Pin configuration of built-in PROM version (continued)55

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MITSUBISHI MICROCOMPUTERS

4250 Group

SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER

(1) PROM mode

The 4250 Group has a function to serially input/output thecommand codes, addresses, and data required for operation(e.g. read and program) on the built-in PROM using only afew pins. This mode can be selected by setting pins SDA (serialdata input/output), SCLK (serial clock input), and PGM to “H”after connecting wires as shown in Figure 32 and poweringon the VDD pin, and then applying 12 V to the VPP pin.

In the PROM mode, three types of software commands (read,program, and program verify) can be used.

Clock-synchronous serial I/O is used, beginning from the LSB(LSB first). Use the special-purpose serial programmer whenperforming serial read/program.

Refer to the Mitsubishi Data Book “DEVELOPMENTSUPPORT TOOLS FOR MICROCOMPUTERS” about theserial programmer (serial programmer and control software,etc.) for the Mitsubishi single-chip microcomputers.(2) Notes on handling

󰃀A high-voltage is used for writing. Take care that overvoltageis not applied. Take care especially at turning on the power.󰃁For the One Time PROM version shipped in blank,Mitsubishi Electric corp. does not perform PROM writingtest and screening in the assembly process and followingprocesses. In order to improve reliability after writing,performing writing and test according to the flow shown inFigure 33 before using is recommended (Products shippedin blank: PROM contents is not written in factory whenshipped)

Writing with PROM programmerScreening (Leave at 150 °C for 40 hours) (Note)Verify test with PROM programmerFunction test in target deviceNote: Since the screening temperature is higher than storage temperature, never expose the microcomputer to 150°C exceeding 100 hours.Fig. 33 Flow of writing and test of the product shipped inblank

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MITSUBISHI MICROCOMPUTERS

4250 Group

SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER

Keep safety first in your circuit designs!•Mitsubishi Electric Corporation puts the maximum effort into making semiconductor products better and more reliable, but there is always the possibility that trouble may occur with them. Trouble withsemiconductors may lead to personal injury, fire or property damage. Remember to give due consideration to safety when making your circuit designs, with appropriate measures such as (i) placement ofsubstitutive, auxiliary circuits, (ii) use of non-flammable material or (iii) prevention against any malfunction or mishap.Notes regarding these materials•••These materials are intended as a reference to assist our customers in the selection of the Mitsubishi semiconductor product best suited to the customer’s application; they do not convey any license under anyintellectual property rights, or any other rights, belonging to Mitsubishi Electric Corporation or a third party.Mitsubishi Electric Corporation assumes no responsibility for any damage, or infringement of any third-party’s rights, originating in the use of any product data, diagrams, charts or circuit application examplescontained in these materials.All information contained in these materials, including product data, diagrams and charts, represent information on products at the time of publication of these materials, and are subject to change by MitsubishiElectric Corporation without notice due to product improvements or other reasons. It is therefore recommended that customers contact Mitsubishi Electric Corporation or an authorized Mitsubishi Semiconductorproduct distributor for the latest product information before purchasing a product listed herein.Mitsubishi Electric Corporation semiconductors are not designed or manufactured for use in a device or system that is used under circumstances in which human life is potentially at stake. Please contactMitsubishi Electric Corporation or an authorized Mitsubishi Semiconductor product distributor when considering the use of a product contained herein for any specific purposes, such as apparatus or systems fortransportation, vehicular, medical, aerospace, nuclear, or undersea repeater use.The prior written approval of Mitsubishi Electric Corporation is necessary to reprint or reproduce in whole or in part these materials.If these products or technologies are subject to the Japanese export control restrictions, they must be exported under a license from the Japanese government and cannot be imported into a country other than theapproved destination.Any diversion or reexport contrary to the export control laws and regulations of Japan and/or the country of destination is prohibited.Please contact Mitsubishi Electric Corporation or an authorized Mitsubishi Semiconductor product distributor for further details on these materials or the products contained therein.••••© 1997 MITSUBISHI ELECTRIC CORP.KI-9711 Printed in Japan (ROD) IINew publication, effective Nov. 1997.

Specifications subject to change without notice.

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REVISION DESCRIPTION LIST

Rev.No.1.0

First Edition

4250 GROUP DATA SHEET

Revision Description

Rev.date971130

(1/1)

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