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MFEATURES
93LC46/56/66BLOCK DIAGRAMVCCVSS1K/2K/4K 2.0V Microwire® Serial EEPROM•Single supply with programming operation down to 2.0V (Commercial only)•Low power CMOS technology-1 mA active current typical
-5 µA standby current (typical) at 3.0V•ORG pin selectable memory configuration
-128 x 8 or 64 x 16-bit organization (93LC46)-256 x 8 or 128 x 16-bit organization(93LC56)-512 x 8 or 256 x 16-bit organization(93LC66)•Self-timed ERASE and WRITE cycles(including auto-erase)
•Automatic ERAL before WRAL
•Power on/off data protection circuitry•Industry standard 3-wire serial I/O
•Device status signal during ERASE/WRITE cycles•Sequential READ function
•10,000,000 ERASE/WRITE cycles guaranteed on 93LC56 and 93LC66
•1,000,000 E/W cycles guaranteed on 93LC46•Data retention > 200 years
•8-pin PDIP/SOIC and 14-pin SOIC package(SOIC in JEDEC and EIAJ standards)•Temperature ranges supported-Commercial (C):0°Cto+70°C-Industrial (I):-40°Cto+85°C
MEMORYARRAYADDRESSDECODERADDRESSCOUNTERDATA REGISTERDIMODEDECODELOGICOUTPUTBUFFERDOCSCLKCLOCKGENERATORDESCRIPTION
The Microchip Technology Inc. 93LC46/56/66 are 1K,2K, and 4K low-voltage serial Electrically ErasablePROMs. The device memory is configured as x8 or x16bits, depending on the ORG pin setup. AdvancedCMOS technology makes these devices ideal forlow-power, nonvolatile memory applications. The93LC46/56/66 is available in standard 8-pin DIP and 8/14-pin surface mount SOIC packages. The 93LC46X/56X/66X are only offered in an “SN” package.
PACKAGE TYPESSOICNC1234567141312111098NCVccNUNCORGVSSNCDIPCSCLKDIDO18VCCNUORGVSS1SOICCSCLKDIDO8VCCNUORGVSSNUVCCCSCLK1SOIC8ORGVSSDODICSCLKNCDIDONC93LC5693LC6693LC4693LC5693LC6693LC4693LC5693LC6693LC46X93LC56X93LC66X234765234765234765© 1997 Microchip Technology Inc.DS11168L-page 1
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93LC46/56/66
1.0
1.1
ELECTRICAL
CHARACTERISTICS
Maximum Ratings*PIN function Table
NameCSCLKDIDOVSSORGNUNCVCC
Function
Chip Select
Serial Data ClockSerial Data InputSerial Data OutputGround
Memory ConfigurationNot UtilizedNo ConnectPower Supply
Vcc...................................................................................7.0VAll inputs and outputs w.r.t. VSS ...............-0.6V to Vcc +1.0VStorage temperature.....................................-65˚C to +150˚CAmbient temp. with power applied.................-65˚C to +125˚CSoldering temperature of leads (10 seconds).............+300˚CESD protection on all pins................................................4 kV
*Notice: Stresses above those listed under “Maximum ratings” maycause permanent damage to the device. This is a stress rating only andfunctional operation of the device at those or any other conditionsabove those indicated in the operational listings of this specification isnot implied. Exposure to maximum rating conditions for extended peri-ods may affect device reliability.
TABLE 1-1DC AND AC ELECTRICAL CHARACTERISTICS
Commercial (C):Vcc = +2.0V to +6.0V(C):Tamb = 0˚C to +70˚CIndustrial (I):Vcc = +2.5V to +6.0V(I):Tamb = -40˚C to +85˚CSymbolMin.Max.UnitsConditions
Parameter
High level input voltageLow level input voltageLow level output voltageHigh level output voltageInput leakage currentOutput leakage currentPin capacitance(all inputs/outputs)Operating current Standby currentClock frequencyClock high timeClock low timeChip select setup timeChip select hold timeChip select low timeData input setup timeData input hold timeData output delay timeData output disable timeStatus valid timeProgram cycle timeEndurance93LC4693LC56/66
Note 1:
2:3:4:
VIH1VIH2VIL1VIL2VOL1VOL2VOH1VOH2ILIILOCIN, COUTICC read ICC writeICCSFCLKTCKHTCKLTCSSTCSHTCSLTDISTDIHTPDTCZTSVTWCTECTWL——
2.00.7 Vcc-0.3-0.3——2.4Vcc-0.2-10-10—————250250500250100100——————1M10M
Vcc +1Vcc +10.80.2 Vcc 0.40.2——101071 50031003021———————400100500101530——
VVVVVVVVµAµApFmAµAmAµAµAMHzMHznsnsnsnsnsnsnsnsnsnsmsmsmscycles
VCC ≥ 2.7VVCC < 2.7VVCC ≥ 2.7VVCC < 2.7V
IOL = 2.1 mA; Vcc = 4.5VIOL =100 µA; Vcc = Vcc Min.IOH = -400 µA; Vcc = 4.5VIOH = -100 µA; Vcc = Vcc Min.VIN = 0.1V to VccVOUT = 0.1V to Vcc
VIN/VOUT = 0 V (Notes 1 & 3)Tamb = +25°C, FCLK = 1 MHz FCLK = 2 MHz; Vcc = 6.0VFCLK = 1 MHz; Vcc = 3.0V
FCLK = 2 MHz; Vcc = 6.0V (Note 3)CLK = CS = 0V; Vcc = 6.0VCLK = CS = 0V; Vcc = 3.0V Vcc ≥ 4.5VVcc < 4.5V
Relative to CLKRelative to CLKRelative to CLKRelative to CLKCL = 100 pFCL = 100 pF (Note 3)CL = 100 pFERASE/WRITE mode (Note 2)ERAL modeWRAL mode
25°C, Vcc = 5.0V, Block Mode (Note 4)
This parameter is tested at Tamb = 25˚C and FCLK = 1 MHz.Typical program cycle time is 4 ms per word.
This parameter is periodically sampled and not 100% tested.
This application is not tested but guaranteed by characterization. For endurance estimates in a specific applica-tion, please consult the Total Endurance Model which can be obtained on our BBS or website.
DS11168L-page 2© 1997 Microchip Technology Inc.元器件交易网www.cecb2b.com
93LC46/56/66
2.0
2.1
PIN DESCRIPTION
Chip Select (CS)2.3Data In (DI)Data In (DI) is used to clock in a START bit, opcode,address, and data synchronously with the CLK input.
A high level selects the device. A low level deselects thedevice and forces it into standby mode. However, a pro-gramming cycle which is already initiated and/or inprogress will be completed, regardless of the CS inputsignal. If CS is brought low during a program cycle, thedevice will go into standby mode as soon as the pro-gramming cycle is completed.
CS must be low for 250 ns minimum (TCSL) betweenconsecutive instructions. If CS is low, the internal con-trol logic is held in a RESET status.
2.4Data Out (DO)Data Out (DO) is used in the READ mode to output datasynchronously with the CLK input (TPD after the posi-tive edge of CLK).
This pin also provides READY/BUSY status informationduring ERASE and WRITE cycles. READY/BUSY sta-tus information is available on the DO pin if CS isbrought high after being low for minimum chip selectlow time (TCSL) and an ERASE or WRITE operation hasbeen initiated.
The status signal is not available on DO, if CS is heldlow or high during the entire WRITE or ERASE cycle. Inall other cases DO is in the HIGH-Z mode. If status ischecked after the ERASE/WRITE cycle, a pull-upresistor on DO is required to read the READY signal.
2.2Serial Clock (CLK)The Serial Clock (CLK) is used to synchronize the com-munication between a master device and the 93LCXX.Opcodes, addresses, and data bits are clocked in onthe positive edge of CLK. Data bits are also clocked outon the positive edge of CLK.
CLK can be stopped anywhere in the transmissionsequence (at high or low level) and can be continuedanytime with respect to clock high time (TCKH) andclock low time (TCKL). This gives the controlling masterfreedom in preparing the opcode, address, and data.CLK is a “Don't Care” if CS is low (device deselected).If CS is high, but the START condition has not beendetected, any number of clock cycles can be receivedby the device without changing its status (i.e., waitingfor a START condition).
CLK cycles are not required during the self-timedWRITE (i.e., auto ERASE/WRITE) cycle.
After detecting a START condition, the specified num-ber of clock cycles (respectively low to high transitionsof CLK) must be provided. These clock cycles arerequired to clock in all required opcodes, addresses,and data bits before an instruction is executed(Table 2-1 to Table 2-6). CLK and DI then become don'tcare inputs waiting for a new START condition to bedetected.Note:CS must go low between consecutiveinstructions.2.5Organization (ORG)When ORG is tied to VSS, the (x8) memory organiza-tion is selected. When ORG is connected to Vcc orfloated, the (x16) memory organization is selected.ORG can only be floated for clock speeds of 1 MHz orless for the (X16) memory organization. For clockspeeds greater than 1 MHz, ORG must be tied to Vccor VSS.
© 1997 Microchip Technology Inc.DS11168L-page 3元器件交易网www.cecb2b.com
93LC46/56/66
INSTRUCTION SET FOR 93LC46: ORG = 0 (X 8 ORGANIZATION)
SB1111111
Opcode11000000100100
Address
A6 A5 A4 A3 A2 A1 A01 0 X X X X X0 0 X X X X X1 1 X X X X X A6 A5 A4 A3 A2 A1 A0A6 A5 A4 A3 A2 A1 A00 1 X X X X X
Data In —————D7 - D0D7 - D0
Data Out(RDY/BSY)(RDY/BSY)HIGH-ZHIGH-ZD7 - D0(RDY/BSY)(RDY/BSY)Req. CLK Cycles
10101010181818
InstructionERASEERALEWDSEWENREADWRITEWRAL
TABLE 2-1
TABLE 2-2
InstructionERASEERALEWDSEWENREADWRITEWRAL
INSTRUCTION SET FOR 93LC46: ORG = 1 (X 16 ORGANIZATION)
SB1111111
Opcode11000000100100
AddressA5 A4 A3 A2 A1 A01 0 X X X X0 0 X X X X1 1 X X X XA5 A4 A3 A2 A1 A0A5 A4 A3 A2 A1 A00 1 X X X X
Data In —————D15 - D0D15 - D0
Data Out(RDY/BSY)(RDY/BSY)HIGH-ZHIGH-ZD15 - D0(RDY/BSY)(RDY/BSY)Req. CLK Cycles
9999252525
TABLE 2-3
InstructionERASEERALEWDSEWENREADWRITEWRAL
INSTRUCTION SET FOR 93LC56: ORG = 0 (X 8 ORGANIZATION)
SB1111111
Opcode11000000100100
Address
X A7 A6 A5 A4 A3 A2 A1 A01 0 X X X X X X X0 0 X X X X X X X1 1 X X X X X X X X A7 A6 A5 A4 A3 A2 A1 A0X A7 A6 A5 A4 A3 A2 A1 A00 1 X X X X X X X
Data In —————D7 - D0D7 - D0
Data Out(RDY/BSY)(RDY/BSY)HIGH-ZHIGH-ZD7 - D0(RDY/BSY)(RDY/BSY)Req. CLK Cycles
12121212202020
TABLE 2-4
InstructionERASEERALEWDSEWENREADWRITEWRAL
INSTRUCTION SET FOR 93LC56: ORG = 1 (X 16 ORGANIZATION)
SB1111111
Opcode11000000100100
Address
X A6 A5 A4 A3 A2 A1 A01 0 X X X X X X0 0 X X X X X X1 1 X X X X X X X A6 A5 A4 A3 A2 A1 A0X A6 A5 A4 A3 A2 A1 A00 1 X X X X X X
Data In —————D15 - D0D15 - D0
Data Out(RDY/BSY)(RDY/BSY)HIGH-ZHIGH-ZD15 - D0(RDY/BSY)(RDY/BSY)Req. CLK Cycles
11111111272727
TABLE 2-5
InstructionERASEERALEWDSEWENREADWRITEWRAL
INSTRUCTION SET FOR 93LC66: ORG = 0 (X 8 ORGANIZATION)
SB1111111
Opcode11000000100100
Address
A8 A7 A6 A5 A4 A3 A2 A1 A01 0 X X X X X X X0 0 X X X X X X X1 1 X X X X X X X A8 A7 A6 A5 A4 A3 A2 A1 A0A8 A7 A6 A5 A4 A3 A2 A1 A00 1 X X X X X X X
Data In —————D7 - D0D7 - D0
Data Out(RDY/BSY)(RDY/BSY)HIGH-ZHIGH-ZD7 - D0(RDY/BSY)(RDY/BSY)Req. CLK Cycles
12121212202020
TABLE 2-6
InstructionREADEWENERASEERALWRITEWRALEWDS
INSTRUCTION SET FOR 93LC66: ORG = 1 (X 16 ORGANIZATION)
SB1111111
Opcode10001100010000
Address
A7 A6 A5 A4 A3 A2 A1 A01 1 X X X X X X A7 A6 A5 A4 A3 A2 A1 A01 0 X X X X X XA7 A6 A5 A4 A3 A2 A1 A00 1 X X X X X X0 0 X X X X X X
Data In ————D15 - D0D15 - D0
—
Data OutD15 - D0High-Z(RDY/BSY)(RDY/BSY)(RDY/BSY)(RDY/BSY)High-Z
Req. CLK Cycles
27111111272711
DS11168L-page 4© 1997 Microchip Technology Inc.元器件交易网www.cecb2b.com
93LC46/56/66
3.2
Data In (DI) and Data Out (DO)It is possible to connect the Data In (DI) and Data Out(DO) pins together. However, with this configuration, ifA0 is a logic-high level, it is possible for a “bus conflict”to occur during the “dummy zero” that precedes theREAD operation. Under such a condition the voltagelevel seen at DO is undefined and will depend upon therelative impedances of Data Out, and the signal sourcedriving A0. The higher the current sourcing capability ofA0, the higher the voltage at the DO pin.
3.0FUNCTIONAL DESCRIPTION
When it is connected to ground, the (x8) organization isselected. When the ORG pin is connected to Vcc, the(x16) organization is selected. Instructions, addressesand write data are clocked into the DI pin on the risingedge of the clock (CLK). The DO pin is normally held ina HIGH-Z state, except when reading data from thedevice or when checking the READY/BUSY status dur-ing a programming operation. The READY/BUSYstatus can be verified during an ERASE/WRITE opera-tion by polling the DO pin; DO low indicates that pro-gramming is still in progress, while DO high indicatesthe device is ready. The DO will enter the HIGH-Z stateon the falling edge of the CS.
3.3Data Protection3.1START ConditionThe START bit is detected by the device if CS and DIare both high with respect to the positive edge of CLKfor the first time.
Before a START condition is detected, CS, CLK, and DImay change in any combination (except to that of aSTART condition), without resulting in any device oper-ation (READ, WRITE, ERASE, EWEN, EWDS, ERAL,and WRAL). As soon as CS is high, the device is nolonger in the standby mode.
An instruction following a START condition will only beexecuted if the required amount of opcodes,addresses, and data bits for any particular instruction isclocked in.
After execution of an instruction (i.e., clock in or out ofthe last required address or data bit) CLK and DIbecome don't care bits until a new START condition isdetected.
During power-up, all programming modes of operationare inhibited until Vcc has reached a level greater than1.4V. During power-down, the source data protectioncircuitry acts to inhibit all programming modes whenVcc has fallen below 1.4V at nominal conditions.The ERASE/WRITE Disable (EWDS) and ERASE/WRITE Enable (EWEN) commands give additional pro-tection against accidentally programming during nor-mal operation.
After power-up, the device is automatically in theEWDS mode. Therefore, an EWEN instruction must beperformed before any ERASE or WRITE instruction canbe executed.
FIGURE 3-1:CSSYNCHRONOUS DATA TIMINGVIHVILVIHTCSSTCKHTCKLTCSHCLKVILTDISVIHDIVILTPDDO (READ)VOHVOLTSVSTATUS VALIDTCZTPDTCZTDIHDO VOH(PROGRAM)VOL© 1997 Microchip Technology Inc.DS11168L-page 5元器件交易网www.cecb2b.com
93LC46/56/66
3.4
ERASE3.5
Erase All (ERAL)The Erase All (ERAL) instruction will erase the entirememory array to the logical “1” state. The ERAL cycleis identical to the ERASE cycle except for the differentopcode. The ERAL cycle is completely self-timed andcommences at the falling edge of the CS. Clocking ofthe CLK pin is not necessary after the device hasentered the self clocking mode. The ERAL instruction isguaranteed at Vcc = +4.5V to +6.0V.
The DO pin indicates the READY/BUSY status of thedevice if CS is brought high after a minimum of 250 nslow (TCSL) and before the entire write cycle is complete.The ERAL cycle takes 15 ms maximum (8 ms typical).
The ERASE instruction forces all data bits of the spec-ified address to the logical “1” state. CS is brought lowfollowing the loading of the last address bit. This fallingedge of the CS pin initiates the self-timed programmingcycle.
The DO pin indicates the READY/BUSY status of thedevice if CS is brought high after a minimum of 250 nslow (TCSL). DO at logical “0” indicates that program-ming is still in progress. DO at logical “1” indicates thatthe register at the specified address has been erasedand the device is ready for another instruction.The ERASE cycle takes 4 ms per word (Typical).
FIGURE 3-2:CSERASE TIMINGTCSLCHECK STATUSSTANDBYCLKDI111AnAn-1An-2• • •A0TSVTCZTRI-STATEDOTRI-STATEBUSYREADYTWCFIGURE 3-3:CSERAL TIMINGTCSLCHECK STATUSSTANDBYCLKDI10010TSVTCZTRI-STATEBUSYREADYDOTRI-STATETECGuarantee at Vcc = +4.5V to +6.0V.DS11168L-page 6© 1997 Microchip Technology Inc.元器件交易网www.cecb2b.com
93LC46/56/66
3.7
READThe READ instruction outputs the serial data of theaddressed memory location on the DO pin. A dummyzero bit precedes the 8-bit (x8 organization) or 16-bit(x16 organization) output string. The output data bitswill toggle on the rising edge of the CLK and are stableafter the specified time delay (TPD.). Sequential read ispossible when CS is held high. The memory data willautomatically cycle to the next register and outputsequentially.
3.6
ERASE/WRITE Disable and Enable (EWEN, EWDS)The 93LC46/56/66 powers up in the ERASE/WRITEDisable (EWDS) state. All programming modes mustbe preceded by an ERASE/WRITE Enable (EWEN)instruction. Once the EWEN instruction is executed,programming remains enabled until an EWDS instruc-tion is executed or VCC is removed from the device. Toprotect against accidental data disturb, the EWDSinstruction can be used to disable all ERASE/WRITEfunctions and should follow all programming opera-tions. Execution of a READ instruction is independentof both the EWDS and EWEN instructions.
FIGURE 3-4:CSEWDS TIMING TCSLCLKDI10 00 0X• • •XFIGURE 3-5:CSEWEN TIMING TCSLCLKDI10 01 1X• • •XFIGURE 3-6:CSREAD TIMINGTCSLCLKDI1 10• An• • •A0DO®TRI-STATETRI-STATE™0Dx• • •D0Dx*• • •D0Dx*• • •D0TRI-STATE is a registered trademark of National Semiconductor Incorporated.Tri-State is a trademark of National Semiconductor.© 1997 Microchip Technology Inc.DS11168L-page 7元器件交易网www.cecb2b.com
93LC46/56/66
3.8
WRITE3.9
Write All (WRAL)The Write All (WRAL) instruction will write the entirememory array with the data specified in the command.The WRAL cycle is completely self-timed and com-mences at the falling edge of the CS. Clocking of theCLK pin is not necessary after the device has enteredthe self clocking mode. The WRAL command doesinclude an automatic ERAL cycle for the device. There-fore, the WRAL instruction does not require an ERALinstruction, but the chip must be in the EWEN status.The WRAL instruction is guaranteed at VCC = +4.5V to+6.0V.
The DO pin indicates the READY/BUSY status of thedevice if CS is brought high after a minimum of 250 nslow (TCSL).
The WRAL cycle takes 30 ms maximum (16 ms typical).
The WRITE instruction is followed by 8 bits (or by 16bits) of data which are written into the specifiedaddress. After the last data bit is put on the DI pin, CSmust be brought low before the next rising edge of theCLK clock. This falling edge of CS initiates the self-timed auto-erase and programming cycle.
The DO pin indicates the READY/BUSY status of thedevice, if CS is brought high after a minimum of 250 nslow (TCSL) and before the entire write cycle is complete.DO at logical “0” indicates that programming is still inprogress. DO at logical “1” indicates that the register atthe specified address has been written with the dataspecified and the device is ready for another instruc-tion.
The WRITE cycle takes 4 ms per word (Typical).
FIGURE 3-7:CSWRITE TIMINGTCSLSTANDBYCLKDI101•An• • •A0Dx• • •D0DOTRI-STATEBUSYREADYTRI_STATETWCFIGURE 3-8:CSWRAL TIMINGTCSLSTANDBYCLKDI10001X• • •XDx• • •D0DOTRI-STATEBUSYREADYTRI-STATETWLGuarantee at Vcc = +4.5V to +6.0V.DS11168L-page 8© 1997 Microchip Technology Inc.元器件交易网www.cecb2b.com
93LC46/56/66
NOTES:
© 1997 Microchip Technology Inc.DS11168L-page 9元器件交易网www.cecb2b.com
93LC46/56/66
NOTES:
DS11168L-page 10© 1997 Microchip Technology Inc.元器件交易网www.cecb2b.com
93LC46/56/66
93LC46/56/66 PRODUCT IDENTIFICATION SYSTEM
To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office..93LC46/56/66—/PP=Plastic DIP (300 mil Body), 8-leadPackage:SL=Plastic SOIC (107 mil Body), 14-leadSN=Plastic SOIC (150 mil Body), 8-leadSM=Plastic SOIC (207 mil Body), 8-leadTemperature Range:Blank=0˚C to +70˚CI=–40˚C to +85˚C93LC4693LC46T93LC46X93LC46XT93LC5693LC56TDevice:93LC56X93LC56XT93LC6693LC66T93LC66X93LC66XT1K Microwire Serial EEPROM1K Microwire Serial EERPOM, Tape and Reel1K Microwire Serial EEPROM in alternate pinouts (SN package only)1K Microwire Serial EEPROM in alternate pinouts, Tape and Reel (SN package only)2K Microwire Serial EEPROM2K Microwire Serial EERPOM, Tape and Reel2K Microwire Serial EEPROM in alternate pinouts (SN package only)2K Microwire Serial EEPROM in alternate pinouts, Tape and Reel (SN package only)4K Microwire Serial EEPROM4K Microwire Serial EERPOM, Tape and Reel4K Microwire Serial EEPROM in alternate pinouts (SN package only)4K Microwire Serial EEPROM in alternate pinouts, Tape and Reel (SN package only)Sales and SupportData Sheets
Products supported by a preliminary Data Sheet may have an errata sheet describing minor operational differences and recom-mended workarounds. To determine if an errata sheet exists for a particular device, please contact one of the following:1.Your local Microchip sales office
2.The Microchip Corporate Literature Center U.S. FAX: (602) 786-7277
3.The Microchip’s Bulletin Board, via your local CompuServe number (CompuServe membership NOT required).
© 1997 Microchip Technology Inc.DS11168L-page 11
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Printed on recycled paper.
Information contained in this publication regarding device applications and the like is intended for suggestion only and may be superseded by updates. No representation orwarranty is given and no liability is assumed by Microchip Technology Incorporated with respect to the accuracy or use of such information, or infringement of patents or otherintellectual property rights arising from such use or otherwise. Use of Microchip’s products as critical components in life support systems is not authorized except with expresswritten approval by Microchip. No licenses are conveyed, implicitly or otherwise, under any intellectual property rights. The Microchip logo and name are registered trademarksof Microchip Technology Inc. in the U.S.A. and other countries. All rights reserved. All other trademarks mentioned herein are the property of their respective companies.DS11168L-page 12Preliminary© 1997 Microchip Technology Inc.
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