93C56B资料

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MFEATURES

93C56A/BPACKAGE TYPEPDIPCSCLKDIDO1234VCC8765NCNCVSS2K 5.0V Automotive Temperature Microwire® Serial EEPROM•Single supply 5.0V operation•Low power CMOS technology-1 mA active current (typical)

-1 µA standby current (maximum)•256 x 8 bit organization (93C56A)•128 x 16 bit organization (93C56B)

•Self-timed ERASE and WRITE cycles (including auto-erase)

•Automatic ERAL before WRAL

•Power on/off data protection circuitry•Industry standard 3-wire serial interface•Device status signal during ERASE/WRITE cycles

•Sequential READ function

•100,000 E/W cycles guaranteed •Data retention > 200 years

•8-pin PDIP and SOIC packages

•Available for the following temperature ranges:-Automotive (E): -40°Cto+125°C

93C56A/BSOICCSCLKDIDO18VCCNCNCVSS93C56A/B234765BLOCK DIAGRAMMEMORYARRAYADDRESSDECODERDESCRIPTION

The Microchip Technology Inc. 93C56A/B is a 2K-bit,low-voltage serial Electrically Erasable PROM. Thedevice memory is conﬁgured as 256 x 8 bits (93C56A)or 128 x 16 bits (93C56B). Advanced CMOS technol-ogy makes this device ideal for low-power, nonvolatilememory applications. The 93C56A/B is available instandard 8-pin DIP and surface mount SOIC packages.This device is only recommeded for 5V automotivetemperature applications. For all commercial andindustrial applications, the 93LC56A/B is recom-mended.

ADDRESSCOUNTERDATA REGISTERDIMEMORYDECODELOGICCLOCKGENERATORVCCVSSOUTPUT BUFFERDOCSCLKMicrowire is a registered trademark of National Semiconductor.© 1998 Microchip Technology Inc.PreliminaryDS21206B-page 1

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93C56A/B

1.0

1.1

ELECTRICAL

CHARACTERISTICS

Maximum Ratings*TABLE 1-1:

NameCSCLKDIDOVSSNCVCC

PIN FUNCTION TABLE

Function

Chip SelectSerial Data ClockSerial Data InputSerial Data OutputGroundNo ConnectPower Supply

VCC...................................................................................7.0VAll inputs and outputs w.r.t. VSS ................-0.6V to Vcc +1.0V

Storage temperature.....................................-65°C to +150°CAmbient temp. with power applied.................-65°C to +125°CSoldering temperature of leads (10 seconds).............+300°CESD protection on all pins................................................4 kV

*Notice: Stresses above those listed under “Maximum ratings” maycause permanent damage to the device. This is a stress rating only andfunctional operation of the device at those or any other conditionsabove those indicated in the operational listings of this speciﬁcation isnot implied. Exposure to maximum rating conditions for extended peri-ods may affect device reliability.

TABLE 1-2:DC AND AC ELECTRICAL CHARACTERISTICS

All parameters apply over the Automotive (E)VCC = +4.5V to +5.5VTamb = -40°C to +125°Cspeciﬁed operating ranges unless otherwise noted

Parameter

High level input voltageLow level input voltageLow level output voltageHigh level output voltageInput leakage currentOutput leakage currentPin capacitance(all inputs/outputs)Operating current Standby currentClock frequencyClock high timeClock low timeChip select setup timeChip select hold timeChip select low timeData input setup timeData input hold timeData output delay timeData output disable timeStatus valid timeProgram cycle timeEndurance

SymbolVIHVILVOLVOHILIILOCIN, COUTICC writeICC read ICCSFCLKTCKHTCKLTCSSTCSHTCSLTDISTDIHTPDTCZTSVTWCTECTWL—

Min.2.0-0.3—2.4-10-10—————250250500250100100——————100K

Max.VCC +10.80.4—101071.51 12———————4001005002615—

UnitsVVVVµAµApFmAmAµAMHznsnsnsnsnsnsnsnsnsnsmsmsmscycles

Relative to CLKRelative to CLKCL = 100 pFCL = 100 pF (Note 2)CL = 100 pF

ERASE/WRITE modeERAL modeWRAL mode

25°C, VCC = 5.0V, Block Mode (Note 3)Relative to CLKRelative to CLKCS = VSS

IOL = 2.1 mA; VCC = 4.5VIOH = -400 µA; VCC = 4.5VVIN = VSS to VCCVOUT = VSS to VCC

VIN/VOUT = 0 V (Notes 1 & 2)Tamb = +25°C, FCLK = 1 MHz (Note 2)

Conditions

Note 1:This parameter is tested at Tamb = 25°C and FCLK = 1 MHz.

2:This parameter is periodically sampled and not 100% tested.

3:This application is not tested but guaranteed by characterization. For endurance estimates in a speciﬁc application, please consult the Total Endurance Model which may be obtained on Microchip’s BBS or web-site.

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93C56A/B

CLK cycles are not required during the self-timedWRITE (i.e., auto ERASE/WRITE) cycle.

After detecting a START condition, the speciﬁed num-ber of clock cycles (respectively low to high transitionsof CLK) must be provided. These clock cycles arerequired to clock in all required opcode, address, anddata bits before an instruction is executed (Table 2-1

and Table 2-2). CLK and DI then become don't care

inputs waiting for a new START condition to bedetected.Note:CS must go low between consecutiveinstructions.2.0

2.1

PIN DESCRIPTION

Chip Select (CS)A high level selects the device. A low level deselectsthe device and forces it into standby mode. However, aprogramming cycle which is already in progress will becompleted, regardless of the CS input signal. If CS isbrought low during a program cycle, the device will gointo standby mode as soon as the programming cycleis completed.

CS must be low for 250 ns minimum (TCSL) betweenconsecutive instructions. If CS is low, the internal con-trol logic is held in a RESET status.

2.3Data In (DI)2.2Serial Clock (CLK)The Serial Clock is used to synchronize the communi-cation between a master device and the 93C56A/B.Opcode, address, and data bits are clocked in on thepositive edge of CLK. Data bits are also clocked out onthe positive edge of CLK.

CLK can be stopped anywhere in the transmissionsequence (at high or low level) and can be continuedanytime with respect to clock high time (TCKH) andclock low time (TCKL). This gives the controlling masterfreedom in preparing opcode, address, and data.CLK is a “Don't Care” if CS is low (device deselected).If CS is high, but the START condition has not beendetected, any number of clock cycles can be receivedby the device without changing its status (i.e., waitingfor a START condition).

Data In is used to clock in a START bit, opcode,address, and data synchronously with the CLK input.

2.4Data Out (DO)Data Out is used in the READ mode to output data syn-chronously with the CLK input (TPD after the positiveedge of CLK).

This pin also provides READY/BUSY status informa-tion during ERASE and WRITE cycles. READY/BUSYstatus information is available on the DO pin if CS isbrought high after being low for minimum chip selectlow time (TCSL) and an ERASE or WRITE operationhas been initiated. The status signal is not available onDO, if CS is held low during the entire ERASE orWRITE cycle. In this case, DO is in the HIGH-Z mode.If status is checked after the ERASE/WRITE cycle, thedata line will be high to indicate the device is ready..

TABLE 2-1:

ERASEERALEWDSEWENREADWRITEWRAL

1111111

INSTRUCTION SET FOR 93C56A

Address

X101XX0

A7001A7A71

A6XXXA6A6X

A5A4A3A2A1A0XXX

XXX

InstructionSBOpcode

11000000100100

Data In

—————D7 - D0D7-D0

Data Out

(RDY/BSY)(RDY/BSY)HIGH-ZHIGH-ZD7 - D0(RDY/BSY)(RDY/BSY)Req. CLK Cycles

12121212202020

A5A4A3A2A1A0A5A4A3A2A1A0X

TABLE 2-2:

ERASEERALEWDSEWENREADWRITEWRAL

1111111

INSTRUCTION SET FOR 93C56B

Address

X101XX0

A6001A6A61

A5XXXA5A5X

A4XXXA4A4X

A3XXXA3A3X

A2XXXA2A2X

A1XXXA1A1X

A0XXXA0A0X

InstructionSBOpcode

11000000100100

Data In

—————D15 - D0D15 - D0

Data Out

(RDY/BSY)(RDY/BSY)HIGH-ZHIGH-ZD15 - D0(RDY/BSY)(RDY/BSY)Req. CLK Cycles

11111111272727

93C56A/B

3.0

FUNCTIONAL DESCRIPTION

3.2Data IN (DI) and Data Out (DO)Instructions, addresses, and write data are clocked intothe DI pin on the rising edge of the clock (CLK). The DOpin is normally held in a HIGH-Z state except whenreading data from the device, or when checking theREADY/BUSY status during a programming operation.The READY/BUSY status can be veriﬁed during anERASE/WRITE operation by polling the DO pin; DOlow indicates that programming is still in progress, whileDO high indicates the device is ready. The DO will enterthe HIGH-Z state on the falling edge of the CS.

It is possible to connect the Data In (DI) and Data Out(DO) pins together. However, with this conﬁguration, ifA0 is a logic-high level, it is possible for a “bus conﬂict”to occur during the “dummy zero” that precedes theREAD operation. Under such a condition, the voltagelevel seen at DO is undeﬁned and will depend upon therelative impedances of DO and the signal source driv-ing A0. The higher the current sourcing capability of A0,the higher the voltage at the DO pin.

3.1START Condition3.3Data ProtectionThe START bit is detected by the device if CS and DIare both high with respect to the positive edge of CLKfor the ﬁrst time.

Before a START condition is detected, CS, CLK, and DImay change in any combination (except to that of aSTART condition), without resulting in any device oper-ation (READ, WRITE, ERASE, EWEN, EWDS, ERAL,and WRAL). As soon as CS is high, the device is nolonger in the standby mode.

An instruction following a START condition will only beexecuted if the required amount of opcode, addressand data bits for any particular instruction is clocked in.After execution of an instruction (i.e., clock in or out ofthe last required address or data bit) CLK and DIbecome don't care bits until a new START condition isdetected.

During power-up, all programming modes of operationare inhibited until Vcc has reached a level greater than3.8V. During power-down, the source data protectioncircuitry acts to inhibit all programming modes whenVcc has fallen below 3.8V at nominal conditions.The ERASE/WRITE Disable (EWDS) and ERASEWRTE Enable (EWEN) commands give additional pro-tection against accidentally programming during nor-mal operation.

After power-up, the device is automatically in theEWDS mode. Therefore, an EWEN instruction must beperformed before any ERASE or WRITE instructioncan be executed.

FIGURE 3-1:CSSYNCHRONOUS DATA TIMINGVIHVILVIHVILTDISVIHTDIHTCSSTCKHTCKLTCSHCLKDIVILTPDTPDTCZVOHVOLVOHTCZTSVDO(READ)DO(PROGRAM)Note:STATUS VALIDVOLAC Test Conditions: VIL = 0.4V, VIH = 2.4V.DS21206B-page 4Preliminary© 1998 Microchip Technology Inc.元器件交易网www.cecb2b.com

93C56A/B

3.5

Erase All (ERAL)The ERAL instruction will erase the entire memoryarray to the logical “1” state. The ERAL cycle is identicalto the ERASE cycle, except for the different opcode.The ERAL cycle is completely self-timed and com-mences at the rising clock edge of the last address bit.Clocking of the CLK pin is not necessary after thedevice has entered the ERAL cycle.

The DO pin indicates the READY/BUSY status of thedevice, if CS is brought high after a minimum of 250 nslow (TCSL) and before the entire ERAL cycle is com-plete.

3.4ERASEThe ERASE instruction forces all data bits of the spec-iﬁed address to the logical “1” state. This cycle beginson the rising clock edge of the last address bit.The DO pin indicates the READY/BUSY status of thedevice if CS is brought high after a minimum of 250 nslow (TCSL). DO at logical “0” indicates that program-ming is still in progress. DO at logical “1” indicates thatthe register at the speciﬁed address has been erasedand the device is ready for another instruction.

FIGURE 3-2:CSERASE TIMINGTCSLCHECK STATUSCLKDI111ANAN-1AN-2•••A0TSVTCZREADYHIGH-ZTWCDOHIGH-ZBUSYFIGURE 3-3:CSERAL TIMINGTCSLCHECK STATUSCLKDI10010X•••XTSVTCZREADYHIGH-ZTECDOHIGH-ZBUSY© 1998 Microchip Technology Inc.PreliminaryDS21206B-page 5元器件交易网www.cecb2b.com

93C56A/B

3.6

ERASE/WRITE Disable and Enable(EWDS/EWEN)3.7READThe device powers up in the ERASE/WRITE Disable(EWDS) state. All programming modes must be pre-ceded by an ERASE/WRITE Enable (EWEN) instruc-tion. Once the EWEN instruction is executed,programming remains enabled until an EWDS instruc-tion is executed or VCC is removed from the device. Toprotect against accidental data disturbance, the EWDSinstruction can be used to disable all ERASE/WRITEfunctions and should follow all programming opera-tions. Execution of a READ instruction is independentof both the EWEN and EWDS instructions.

The READ instruction outputs the serial data of theaddressed memory location on the DO pin. A dummyzero bit precedes the 8-bit (93C56A) or 16-bit(93C56B) output string. The output data bits will toggleon the rising edge of the CLK and are stable after thespeciﬁed time delay (TPD). Sequential read is possiblewhen CS is held high. The memory data will automati-cally cycle to the next register and output sequentially.

FIGURE 3-4:

READ TIMING

CLKDI

•••A0

HIGH-Z

0Dx•••D0Dx•••D0Dx•••D0

93C56A/B

3.9

Write All (WRAL)The Write All (WRAL) instruction will write the entirememory array with the data speciﬁed in the command.The WRAL cycle is completely self-timed and com-mences at the rising clock edge of the last data bit.Clocking of the CLK pin is not necessary after thedevice has entered the WRAL cycle. The WRAL com-mand does include an automatic ERAL cycle for thedevice. Therefore, the WRAL instruction does notrequire an ERAL instruction but the chip must be in theEWEN status.

The DO pin indicates the READY/BUSY status of thedevice if CS is brought high after a minimum of 250 nslow (TCSL).

3.8WRITEThe WRITE instruction is followed by 8-bits (93C56A)16-bits (93C56B) of data which are written into thespeciﬁed address. After the last data bit is clocked intothe DI pin, the self-timed auto-erase and programmingcycle begins.

The DO pin indicates the READY/BUSY status of thedevice, if CS is brought high after a minimum of 250 nslow (TCSL) and before the entire write cycle is complete.DO at logical “0” indicates that programming is still inprogress. DO at logical “1” indicates that the register atthe speciﬁed address has been written with the dataspeciﬁed and the device is ready for another instruc-tion.

FIGURE 3-7:CSWRITE TIMINGTCSLCLKDI101An•••A0Dx•••D0TSVTCZREADYDOHIGH-ZBUSYHIGH-ZTwcFIGURE 3-8:CSWRAL TIMINGTCSLCLKDI10001X•••XDx•••D0TSVTCZREADYHIGH-ZTWLDOHIGH-ZBUSY© 1998 Microchip Technology Inc.PreliminaryDS21206B-page 7元器件交易网www.cecb2b.com

93C56A/B

NOTES:

93C56A/B

NOTES:

93C56A/B

NOTES:

93C56A/B

93C56A/B PRODUCT IDENTIFICATION SYSTEM

To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales ofﬁce.93C56A/B /PPackage:P=Plastic DIP (300 mil Body), 8-leadSN=Plastic SOIC (150 mil Body), 8-leadE=-40°C to +125°CTemperature Range:93C56ADevice:93C56AT93C56B93C56BT2K Microwire Serial EEPROM (x8)2K Microwire Serial EEPROM (x8) Tape and Reel2K Microwire Serial EEPROM (x16)2K Microwire Serial EEPROM (x16) Tape and ReelSales and SupportData Sheets

Products supported by a preliminary Data Sheet may have an errata sheet describing minor operational differences and recom-mended workarounds. To determine if an errata sheet exists for a particular device, please contact one of the following:1.Your local Microchip sales ofﬁce.

2.The Microchip Corporate Literature Center U.S. FAX: (602) 786-7277.

3.The Microchip’s Bulletin Board, via your local CompuServe number (CompuServe membership NOT required).

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Information contained in this publication regarding device applications and the like is intended for suggestion only and may be superseded by updates. No representation or warranty is given and noliability is assumed by Microchip Technology Incorporated with respect to the accuracy or use of such information, or infringement of patents or other intellectual property rights arising from such useor otherwise. Use of Microchip’s products as critical components in life support systems is not authorized except with express written approval by Microchip. No licenses are conveyed, implicitly orotherwise, under any intellectual property rights. The Microchip logo and name are registered trademarks of Microchip Technology Inc. in the U.S.A. and other countries. All rights reserved. All othertrademarks mentioned herein are the property of their respective companies.DS21206B-page 12Preliminary© 1998 Microchip Technology Inc.

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93C56B资料