Ultralow Power +3.3 V, RS-232
Notebook PC Serial Port Drivers/Receivers
FEATURES
RS-232 compatible
Operates with 3 V or 5 V logic
Ultralow power CMOS: 1.3 mA operation Low power shutdown: 0.2 μA Suitable for serial port mice 116 kbps data rate
1 μF charge pump capacitors
Single +3 V to +3.6 V power supply
Two receivers active in shutdown (ADM560)
APPLICATIONS
Notebook computers Peripherals Modems Printers
Battery-operated equipment
GENERAL DESCRIPTION
The ADM560/ADM561 are four driver/five receiver interface devices designed to meet the EIA-232 standard and operate with a single +3.3 V power supply. The devices feature an on-board dc-to-dc converter, eliminating the need for dual ±5 V power supplies. This dc-to-dc converter contains a voltage doubler and voltage inverter, both of which internally generate ±6.6 V from the input +3.3 V power supply.
The ADM560 and the ADM561 consume only 5 mW making them ideally suited for battery and other power-sensitive appli-cations. A shutdown facility is also provided to reduce the power to 0.66 μW.
The ADM560 contains active low shutdown and an active high receiver enable signal. In shutdown mode, two receivers remain active, thereby allowing monitoring of peripheral devices. This feature allows the device to be shut down until a peripheral
Rev. B
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ADM560/ADM561
FUNCTIONAL BLOCK DIAGRAM
+3.3V INPUT1µF+12C1++3.3VTO +6.6VVCC1110VC314C1–DOUBLERVOLTAGEV+13+1µF0.1µF6.3V1µF+15C2++6.6VV–1710V16C2–INVERTERVOLTAGETO –6.6V+C41µF10VT1IN7T12T1OUTT2IN6T23T2OUTINPUTSCMOSEIA/TIA-232T3IN20T31T3OUTPUTSOUTT4IN21T428T4OUTR1OUT8R19R1INR2OUT5R24R2INOUTPUTSCMOSR3OUT26R327R3INEIA/TIA-232INPUTSR4OUT22R423R4INR5OUT19R518R5INEN (ADM560)24EN (ADM561)GNDADM560/SHDN (ADM560)ADM56125SHDN (ADM561)10100-76650
Figure 1.
device begins communication. The active receivers alert the processor, and then take the ADM560 out of shutdown mode. The ADM561 features active high shutdown and an active low receiver enable. In this device, all receivers are disabled in shutdown.
The ADM560/ADM561 are fabricated using CMOS technology for minimal power consumption. They feature a high level of over-voltage protection and latch-up immunity. The receiver inputs can withstand up to ±25 V levels. The transmitter inputs can be driven from either 3 V or 5 V logic levels. This allows operation in mixed 3 V/5 V power supply systems. The ADM560/ADM561 are packaged in a 28-lead SOIC and a 28-lead SSOP package.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 ©2006 Analog Devices, Inc. All rights reserved.
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ADM560/ADM561
Pin Configuration and Function Descriptions..............................5 Typical Performance Characteristics..............................................6 Theory of Operation.........................................................................8 Circuit Description.......................................................................8 Enable and Shutdown...................................................................8 Outline Dimensions..........................................................................9 Ordering Guide..........................................................................10
TABLE OF CONTENTS
Features..............................................................................................1 Applications.......................................................................................1 Functional Block Diagram..............................................................1 General Description.........................................................................1 Revision History...............................................................................2 Specifications.....................................................................................3 Absolute Maximum Ratings............................................................4 ESD Caution..................................................................................4
REVISION HISTORY
9/06—Rev. A to Rev. B
Updated Format..................................................................Universal Changes to Specifications................................................................3
10/05—Rev. 0 to Rev. A
Updated Format..................................................................Universal Changes to Specifications................................................................3 Update to Outline Dimensions.......................................................9 Changes to Ordering Guide..........................................................10 7/94—Revision 0: Initial Version
Rev. B | Page 2 of 12
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ADM560/ADM561
SPECIFICATIONS
VCC = +3.3 V ± 10%, C1 to C4 = 1 μF, all specifications TMIN to TMAX, unless otherwise noted. Table 1. Parameter Output Voltage Swing VCC Power Supply Current Shutdown Supply Current Input Logic Threshold Low, VINL Input Logic Threshold High, VINH Logic Pull-Up Current EIA-232 Input Voltage Range EIA-232 Input Threshold Low EIA-232 Input Threshold High EIA-232 Input Hysteresis EIA-232 Input Resistance CMOS Output Voltage Low, VOL CMOS Output Voltage High, VOH CMOS Output Leakage Current Output Enable Time Output Disable Time Receiver Propagation Delay TPHL TPLH Transition Region Slew Rate Transmitter Output Resistance RS-232 Output Short-Circuit Current Min ±5.0 ±4 2.4 –25 0.4 3 2.8 300 Typ ±5.5 ±4.5 3.5 3.5 0.2 3 0.8 1.1 0.3 5 +0.05 100 50 0.1 0.5 4.5 ±10 Max 5 5 5 0.4 20 +25 2.4 7 0.4 ±5 1 2 Unit V V mA mA μA V V μA V V V V kΩ V V μA ns ns μs μs V/μs Ω mA Test Conditions/Comments VCC = 3.3 V, three transmitter outputs loaded with 3 kΩ to ground VCC = 3.0 V, all transmitter outputs, loaded with 3 kΩ to ground No load, TIN = VCC No load, TIN = GND SHDN = GND (ADM560), SHDN = VCC (ADM561), TIN = VCC TIN, EN, EN , SHDN, SHDNTIN, EN, EN, SHDN, SHDN TIN = GND IOUT = 1.6 mA IOUT = −40 mA EN = VCC, EN = GND, 0 V ≤ ROUT ≤ VCC RL = 3 kΩ, CL = 2500 pF measured from +3 V to −3 V or −3 V to +3 V VCC = V+ = V− = 0 V, VOUT = ±2 V
Rev. B | Page 3 of 12
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ADM560/ADM561
ABSOLUTE MAXIMUM RATINGS
TA = 25°C, unless otherwise noted. Table 2.
Stresses above those listed under Absolute Maximum Ratings Parameter Rating may cause permanent damage to the device. This is a stress VCC −0.3 V to +6 V
rating only; functional operation of the device at these or any V+ (VCC − 0.3 V) to +14 V
other conditions above those indicated in the operational V− +0.3 V to −14 V
section of this specification is not implied. Exposure to absolute Input Voltages
maximum rating conditions for extended periods may affect TIN −0.3 V to (V+, +0.3 V)
device reliability.
RIN 25 V Output Voltages TOUT (V+, +0.3 V) to (V−, −0.3 V)
ROUT −0.3 V to (VCC + 0.3 V)
Short-Circuit Duration
TOUT Continuous Power Dissipation SSOP 900 mW SOIC 900 mW Operating Temperature Range
Commercial (J Version) 0°C to +70°C Storage Temperature Range −65°C to +150°C
+300°C Lead Temperature
(Soldering, 10 sec)
ESD Rating >2000 V
ESD CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although this product features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.
Rev. B | Page 4 of 12
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ADM560/ADM561
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
T3OUT1T1OUT2T2OUT3R2IN4R2OUT5T2IN6T1IN7R1OUT8R1IN9GND10VCC11C1+12V+13C1–14282726T4OUTR3INR3OUTSHDNENR4INR4OUTT4INT3INR5OUTR5INV–05667-002T3OUT1T1OUT2T2OUT3R2IN4R2OUT5T2IN6T1IN7R1OUT8R1IN9GND10VCC11C1+12V+13C1–14282726T4OUTR3INR3OUTSHDNENR4INR4OUTT4INT3INR5OUTR5INV–C2+05667-012ADM560TOP VIEW(Not to Scale)2524232221201918171615ADM561TOP VIEW(Not to Scale)2524232221201918171615C2–C2+C2–
Figure 2.ADM560 Pin Configuration Figure 3. ADM561 Pin Configuration
Table 3. Pin Function Descriptions Pin No. 2, 3, 1, 28 9, 4, 27, 23, 18 8, 5, 26, 22, 19 7, 6, 20, 21 Mnemonic T1OUT to T4OUT R1IN to R5IN R1OUT to R5OUT T1IN to T4IN Description Transmitter (Driver) Outputs. Typically ±6 V. Receiver Inputs. These inputs accept RS-232 signal levels. An internal 5 kΩ pull-down resistor to GND is connected on each of these inputs. Receiver Outputs. These are 3 V logic levels. Transmitter (Driver) Inputs. These inputs accept 3 V or 5 V logic levels. An internal 400 kΩ pull-up resistor to VCC is connected on each input. Ground Pin. Must be connected to 0 V. Power Supply Input 3.3 V ± 10%. External Capacitor 1 is connected between these pins. Internally Generated Positive Supply. +6.6 V nominal. External Capacitor 2 is connected between these pins. Internally Generated Negative Supply. −6.6 V nominal. Receiver Enable. EN, active high on ADM560. EN, active low on ADM561. Refer to Table 4. Shutdown Control. SHDN, active low on ADM560. SHDN, active high on ADM561. Refer to Table 4. 10 GND 11 VCC 12, 14 C1+, C1− 13 V+ 15, 16 C2+, C2− 17 V− 24 EN/EN 25 SHDN/SHDN Table 4. ADM560/ADM561 Enable and Shutdown Control Normal Operation ADM560 SHDN = 1 EN = 1; receivers active EN = 0; receivers inactive SHDN = 0 EN = 1; Receiver R1 to Receiver R3 inactive EN = 1; Receiver R4 and Receiver R5 active EN = 0; Receiver R1 to Receiver R5 inactive ADM561 SHDN = 0 EN = 0; receivers active EN = 1; receivers inactive SHDN = 1 EN = 0; receivers inactive EN = 1; receivers inactive Shutdown Mode
Rev. B | Page 5 of 12
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ADM560/ADM561
TYPICAL PERFORMANCE CHARACTERISTICS
65160kbps80kbps20kbps4)V( HO3VTA = 25°CV2CC = 3.3V4 TRANSMITTERS LOADEDWITH RC1TO C4 = 1µFL = 5kΩ || CL1500-766050050010001500200025003000LOAD CAPACITANCE (pF)
Figure 4. Transmitter Output Voltage High vs. Load Capacitance
6.25TC1 TO C4 = 1µFA = 25°CVCC = 3.3VTRANSMITTERS UNLOADED5.75)T HIGHVOUT( | TUOT |5.25TOUT LOW600-7664.7550012345| IOUT | (mA)
Figure 5. Transmitter Output Voltage vs. Load Current
10.59.58.57.51 TRANSMITTER)VLOADED( HOV6.5TA = 25°CC1 TO C4 = 1µFTRANSMITTERS LOADED5.5WITH 5kΩ || 2500pF4 TRANSMITTERSLOADED4.5700-7663.5502.53.03.54.04.55.05.5VCC (V)
Figure 6. Transmitter Output Voltage High vs. VCC Rev. B | Page 6 of 12
0TA = 25°CVCC = 3.3V–14 TRANSMITTERS LOADEDWITH RL = 5kΩ || CC1TO C4 = 1µFL–2)V( LO–3V–4160kbps80kbps–58020kbps0-766–650050010001500200025003000LOAD CAPACITANCE (pF)
Figure 7. Transmitter Output Voltage Low vs. Load Capacitance
454035)sµ30/(V E25ATR W20ELS15103 TRANSMITTERSLOADED594 TRANSMITTERS00-LOADED76605050010001500200025003000LOAD CAPACITANCE (pF)
Figure 8. Transmitter Slew Rate vs. Load Capacitance
–3TA = 25°C–4C1TO C4 = 1µFTRANSMITTERS LOADEDWITH 5kΩ || 2500pF–54 TRANSMITTERS)V–6LOADED( LOV–71 TRANSMITTERLOADED–8–9010-766–10502.53.03.54.04.55.05.5VCC (V)
Figure 9. Transmitter Output Voltage Low vs. VCC
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10TA = 25°CVCC = 3.3VC1TO C4 = 1µFALL TRANSMITTERS UNLOADEDADM560/ADM561
V+AND V–EQUALLY LOADEDV+ LOADEDV– LOADEDNO LOAD ON V–NO LOAD ON V+OUTPUT VOLTAGE V+, V– (V)5
05667-0110–5
–10051013152025CURRENT (mA)
Figure 10. V+, V− vs. Load Current
Rev. B | Page 7 of 12
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ADM560/ADM561
Transmitter (Driver) Section
The drivers convert 3 V or 5 V logic input levels into EIA-232 output levels. With VCC = +3.3 V and driving an EIA-232 load, the output voltage swing is typically ±5.5 V.
VCCS1C1S2GND+S4VCCS3V+ = 2VCCC3+THEORY OF OPERATION
The ADM560/ADM561 are RS-232 transmission line drivers/ receivers, and operate from a single +3.3 V supply. This is achieved by integrating step-up voltage converters and level shifting trans-mitters and receivers onto the same chip. CMOS technology is used to keep the power dissipation at an absolute minimum. The ADM560/ADM561 are a modification, enhancement, and improvement to the ADM241L family and its derivatives thereof. These devices are essentially plug-in compatible and do not have materially different applications.
The ADM560/ADM561 contain an internal voltage doubler and a voltage inverter that generates ±6.6 V from the +3.3 V input. Four external 1 μF capacitors are required for the inter-nal voltage converters.
INTERNALOSCILLATOR05667-003
Figure 11. Charge Pump Voltage Double Operation
V+FROMVOLTAGEDOUBLERGNDS1C2S2+S4V– = – (V+)S3GNDC4+CIRCUIT DESCRIPTION
The internal circuitry consists of three main sections. These are as follows: • • •
A charge pump voltage converter. 3 V logic to EIA-232 transmitters. EIA-232 to 3 V logic receivers.
INTERNALOSCILLATOR05667-004
Figure 12. Charge Pump Voltage Inverted Operation
Charge Pump DC-to-DC Voltage Converter
The charge pump voltage converter consists of an oscillator and a switching matrix. The converter generates a ±6.6 V supply from the input +3.3 V level. This is done in two stages using a switched capacitor technique (see Figure 11 and Figure 12). First, the +3.3 V input supply is doubled to +6.6 V using Capacitor C1 as the charge storage element. The +6.6 V level is then inverted to generate −6.6 V using Capacitor C2 as the storage element. Capacitor C3 and Capacitor C4 are used to reduce the output ripple. Their values are not critical and can be reduced if higher levels of ripple are acceptable. The C1 and C2 charge pump capac-itors can also be reduced at the expense of the higher output impedance on the V+ and V− supplies.
The V+ and V− supplies are also used to power external circuitry if the current requirements are small.
Unused inputs can be left unconnected as an internal 400 kΩ pull-up resistor pulls them high forcing the outputs into a low state. The input pull-up resistors typically source 8 μA when grounded, so connect unused inputs to VCC or leave unconnec-ted in order to minimize power consumption.
Receiver Section
The receivers are inverting level shifters; they accept EIA-232 input levels and translate them into 3 V logic output levels. The inputs have internal 5 kΩ pull-down resistors to ground and are also protected against overvoltages of up to ±25 V. The guaranteed switching thresholds are 0.4 V minimum and 2.4 V maximum. Unconnected inputs are pulled to 0 V by the internal 5 kΩ pull-down resistor. This results in a Logic 1 output level for unconnected inputs or for inputs connected to GND.
The receivers have a Schmitt trigger input with a hysteresis level of 0.3 V. This ensures error-free reception for both noisy inputs and for inputs with slow transition times.
ENABLE AND SHUTDOWN
Table 4 shows the truth table for the enable and shutdown control signals. When disabled all receivers are placed in a high impedance state. In shutdown, all transmitters are disa-bled and all receivers on the ADM561 are disabled. On the ADM560, Receiver R4 and Receiver R5 remain enabled in shutdown.
Rev. B | Page 8 of 12
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ADM560/ADM561
OUTLINE DIMENSIONS
10.5010.209.9028155.605.305.001148.207.807.402.00 MAX1.851.751.650.380.22SEATINGPLANE8°4°0°0.250.090.05 MINCOPLANARITY0.100.65 BSC0.950.750.55060106-ACOMPLIANTTO JEDEC STANDARDS MO-150-AH
Figure 13. 28-Lead Shrink Small Outline Package [SSOP]
(RS-28)
Dimensions shown in millimeters
18.10 (0.7126)17.70 (0.6969)28157.60 (0.2992)7.40 (0.2913)11410.65 (0.4193)10.00 (0.3937)0.30 (0.0118)0.10 (0.0039)COPLANARITY0.101.27 (0.0500)BSC0.51 (0.0201)0.31 (0.0122)2.65 (0.1043)2.35 (0.0925)0.75 (0.0295) 45°0.25 (0.0098)8°0°1.27 (0.0500)0.40 (0.0157)SEATINGPLANE0.33 (0.0130)0.20 (0.0079)COMPLIANTTO JEDEC STANDARDS MS-013-AECONTROLLING DIMENSIONSARE IN MILLIMETERS; INCH DIMENSIONS(INPARENTHESES)ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FORREFERENCE ONLYANDARE NOTAPPROPRIATE FOR USE IN DESIGN.060706-A
Figure 14. 28-Lead Standard Small Outline Package [SOIC_W]
Wide Body (RW-28)
Dimensions shown in millimeters and (inches)
Rev. B | Page 9 of 12
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ADM560/ADM561
Package Description
28-Lead Standard Small Outline Package [SOIC_W] 28-Lead Standard Small Outline Package [SOIC_W] 28-Lead Standard Small Outline Package [SOIC_W] 28-Lead Standard Small Outline Package [SOIC_W] 28-Lead Shrink Small Outline Package [SSOP] 28-Lead Shrink Small Outline Package [SSOP] 28-Lead Shrink Small Outline Package [SSOP] 28-Lead Shrink Small Outline Package [SSOP]
28-Lead Standard Small Outline Package [SOIC_W] 28-Lead Standard Small Outline Package [SOIC_W] 28-Lead Standard Small Outline Package [SOIC_W] 28-Lead Standard Small Outline Package [SOIC_W] 28-Lead Shrink Small Outline Package [SSOP] 28-Lead Shrink Small Outline Package [SSOP] 28-Lead Shrink Small Outline Package [SSOP] 28-Lead Shrink Small Outline Package [SSOP]
Package Option RW-28 RW-28 RW-28 RW-28 RS-28 RS-28 RS-28 RS-28 RW-28 RW-28 RW-28 RW-28 RS-28 RS-28 RS-28 RS-28
ORDERING GUIDE
Model ADM560JR
ADM560JR-REEL ADM560JRZ1
ADM560JRZ-REEL1ADM560JRS
ADM560JRS-REEL ADM560JRSZ1 ADM560JRSZ-REEL1ADM561JR
ADM561JR-REEL ADM561JRZ1
ADM561JRZ-REEL1ADM561JRS
ADM561JRS-REEL ADM561JRSZ1
ADM561JRSZ-REEL1
1
Temperature Range 0°C to +70°C 0°C to +70°C 0°C to +70°C 0°C to +70°C 0°C to +70°C 0°C to +70°C 0°C to +70°C 0°C to +70°C 0°C to +70°C 0°C to +70°C 0°C to +70°C 0°C to +70°C 0°C to +70°C 0°C to +70°C 0°C to +70°C 0°C to +70°C
Z = Pb-free part.
Rev. B | Page 10 of 12
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ADM560/ADM561
NOTES
Rev. B | Page 11 of 12
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ADM560/ADM561
NOTES
©2006 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D05667-0-9/06(B)
Rev. B | Page 12 of 12
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