MT41K2G4 – 256 Meg x 4 x 8 banksMT41K1G8 – 128 Meg x 8 x 8 banks
MT41K512M16 – 64 Meg x 16 x 8 banksDescription
DDR3L (1.35V) SDRAM is a low voltage version of theDDR3 (1.5V) SDRAM. Refer to a DDR3 (1.5V) SDRAMdata sheet specifications when running in 1.5V com-patible mode.
•TC of 0°C to +95°C
–64ms, 8192-cycle refresh at 0°C to +85°C–32ms at +85°C to +95°C•Self refresh temperature (SRT)•Automatic self refresh (ASR)•Write leveling
•Multipurpose register•Output driver calibration
Features
•VDD = VDDQ = 1.35V (1.283–1.45V)
•Backward compatible to VDD = VDDQ = 1.5V ±0.075V–Supports DDR3L devices to be backward com-patible in 1.5V applications
•Differential bidirectional data strobe•8n-bit prefetch architecture
•Differential clock inputs (CK, CK#)•8 internal banks
•Nominal and dynamic on-die termination (ODT)for data, strobe, and mask signals
•Programmable CAS (READ) latency (CL)
•Programmable posted CAS additive latency (AL)•Programmable CAS (WRITE) latency (CWL)
•Fixed burst length (BL) of 8 and burst chop (BC) of 4(via the mode register set [MRS])
•Selectable BC4 or BL8 on-the-fly (OTF)•Self refresh mode
Table 1: Key Timing Parameters
Speed Grade-1071-125Note:
Data Rate (MT/s)18661600Options
•Configuration–2 Gig x 4–1 Gig x 8
–512 Meg x 16
•FBGA package (Pb-free) – x4, x8–78-ball (9mm x 13.2mm)•FBGA package (Pb-free) – x16–96-ball (9mm x 14mm)•Timing – cycle time
–1.25ns @ CL = 11 (DDR3-1600)–1.07ns @ CL = 13 (DDR3-1866)•Operating temperature
–Commercial (0°C ≤ TC ≤ +95°C)–Industrial (–40°C ≤ TC ≤ +95°C)•Revision
Marking
2G41G8512M16SNHA-125-107NoneIT:A
Target tRCD-tRP-CL13-13-1311-11-11tRCD (ns)tRP (ns)CL (ns)13.9113.7513.9113.7513.9113.751.Backward compatible to 1600, CL = 11 (-125).
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8Gb_DDR3L.pdf - Rev. C 10/15 EN
PDF: 09005aef8591dc1f8Gb_DDR3L.pdf - Rev. C 10/15 ENFigure 68: Nonconsecutive READ BurstsT0
CK#CKCommandAddressREADBank a,Col nNOPNOPNOPNOPREADBank a,Col bCL = 8 CL = 8 DQS, DQS#DQDOnDObNOPNOPNOPNOPNOPNOPNOPNOPNOPNOPNOPNOPT1
T2
T3
T4
T5
T6
T7
T8
T9
T10
T11
T12
T13
T14
T15
T16
T17
Transitioning DataDon’t Care
Notes:
1.2.3.4.AL = 0, RL = 8.
DO n (or b) = data-out from column n (or column b).
Seven subsequent elements of data-out appear in the programmed order following DO n.Seven subsequent elements of data-out appear in the programmed order following DO b.
Figure 69: READ (BL8) to WRITE (BL8)CK#CKCommand1READNOPNOPNOPNOPNOPWRITENOPNOPNOPNOPNOPNOPNOPNOPNOPtWRtWRT0T1T2T3T4T5T6T7T8T9T10T11T12T13T14T15READ-to-WRITE command delay = RL + tCCD + 2tCK - WLtBL = 4 clocks8Gb: x4, x8, x16 DDR3L SDRAMREAD OperationAddress2Bank,Col ntRPREBank,Col btRPSTtWPREtWPSTDQS, DQS#DQ3
RL = 5DO nDO n + 1DO n + 2DO n + 3DO n + 4DO n + 5DO n + 6DO n + 7DI nDI n + 1DIDI n + 2 n + 3DI n + 4DI n + 5DI n + 6DI n + 7WL = 5Transitioning Data
Don’t Care
Notes:
1.NOP commands are shown for ease of illustration; other commands may be valid at these times.
2.The BL8 setting is activated by either MR0[1:0] = 00 or MR0[1:0] = 01 and A12 = 1 during the READ command at
T0, and the WRITE command at T6.
3.DO n = data-out from column, DI b = data-in for column b.4.BL8, RL = 5 (AL = 0, CL = 5), WL = 5 (AL = 0, CWL = 5).
PDF: 09005aef8591dc1f8Gb_DDR3L.pdf - Rev. C 10/15 ENFigure 70: READ (BC4) to WRITE (BC4) OTFCK#CKCommand1READNOPNOPNOPWRITENOPNOPNOPNOPNOPNOPNOPNOPNOPNOPtWRtWTRT0T1T2T3T4T5T6T7T8T9T10T11T12T13T14T15
NOPREAD-to-WRITE command delay = RL + tCCD/2 + 2tCK - WLtBL = 4 clocksAddress2Bank,Col nBank,Col btRPREtRPSTtWPREtWPSTDQS, DQS#DQ3
RL = 5DOnDOn +1DOn + 2DOn + 3DInDIn + 1DIn + 2DIn + 3WL = 5Transitioning Data
Don’t Care
Notes:
1.NOP commands are shown for ease of illustration; other commands may be valid at these times.
2.The BC4 OTF setting is activated by MR0[1:0] and A12 = 0 during READ command at T0 and WRITE command atT4.
3.DO n = data-out from column n; DI n = data-in from column b.4.BC4, RL = 5 (AL - 0, CL = 5), WL = 5 (AL = 0, CWL = 5).
Figure 71: READ to PRECHARGE (BL8)CK#CKCommandAddressREADBank a,Col ntRTPT0T1T2T3T4T5T6T7T8T9T10T11T12T13T14T15T16T178Gb: x4, x8, x16 DDR3L SDRAMREAD OperationNOPNOPNOPNOPPREBank a,(or all)NOPNOPNOPNOPNOPNOPNOPACTBank a,Row bNOPNOPNOPNOPtRPDQS, DQS#DQtRASDOnDOn + 1DOn + 2DOn + 3DOn + 4DOn + 5DOn + 6DOn + 7Transitioning DataDon’t Care
8Gb: x4, x8, x16 DDR3L SDRAM
WRITE Operation
WRITE Operation
WRITE bursts are initiated with a WRITE command. The starting column and bank ad-dresses are provided with the WRITE command, and auto precharge is either enabled ordisabled for that access. If auto precharge is selected, the row being accessed is pre-charged at the end of the WRITE burst. If auto precharge is not selected, the row willremain open for subsequent accesses. After a WRITE command has been issued, theWRITE burst may not be interrupted. For the generic WRITE commands used in Fig-ure 82 (page 163) through Figure 90 (page 168), auto precharge is disabled.
During WRITE bursts, the first valid data-in element is registered on a rising edge ofDQS following the WRITE latency (WL) clocks later and subsequent data elements willbe registered on successive edges of DQS. WRITE latency (WL) is defined as the sum ofposted CAS additive latency (AL) and CAS WRITE latency (CWL): WL = AL + CWL. Thevalues of AL and CWL are programmed in the MR0 and MR2 registers, respectively. Priorto the first valid DQS edge, a full cycle is needed (including a dummy crossover of DQS,DQS#) and specified as the WRITE preamble shown in Figure 82 (page 163). The halfcycle on DQS following the last data-in element is known as the WRITE postamble.The time between the WRITE command and the first valid edge of DQS is WL clocks±tDQSS. Figure 83 (page 164) through Figure 90 (page 168) show the nominal casewhere tDQSS = 0ns; however, Figure 82 (page 163) includes tDQSS (MIN) and tDQSS(MAX) cases.
Data may be masked from completing a WRITE using data mask. The data mask occurson the DM ball aligned to the WRITE data. If DM is LOW, the WRITE completes normal-ly. If DM is HIGH, that bit of data is masked.
Upon completion of a burst, assuming no other commands have been initiated, the DQwill remain High-Z, and any additional input data will be ignored.
Data for any WRITE burst may be concatenated with a subsequent WRITE command toprovide a continuous flow of input data. The new WRITE command can be tCCD clocksfollowing the previous WRITE command. The first data element from the new burst isapplied after the last element of a completed burst. Figure 83 (page 164) and Figure 84(page 164) show concatenated bursts. An example of nonconsecutive WRITEs is shownin Figure 85 (page 165).
Data for any WRITE burst may be followed by a subsequent READ command after tWTRhas been met (see Figure 86 (page 165), Figure 87 (page 166), and Figure 88(page 167)).
Data for any WRITE burst may be followed by a subsequent PRECHARGE command,providing tWR has been met, as shown in Figure 89 (page 168) and Figure 90(page 168).
Both tWTR and tWR starting time may vary, depending on the mode register settings(fixed BC4, BL8 versus OTF).
PDF: 09005aef8591dc1f
8Gb_DDR3L.pdf - Rev. C 10/15 EN
8Gb: x4, x8, x16 DDR3L SDRAM
WRITE Operation
Figure 80: tWPRE Timing
CK
VTTCK#
tWPRE beginsT1DQS - DQS#
Resulting differential signal relevant for tWPRE specificationtWPRE0VtWPRE endsT2PDF: 09005aef8591dc1f
8Gb_DDR3L.pdf - Rev. C 10/15 EN
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